74ALVC125PW,118

The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Applications

• Direct TTL-level interface
• Partial power-down mode operation

Key features

• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• Overvoltage tolerant inputs to 3.6 V
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD78 Class II.A
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C