74HC595D,118-CN

74HC595D,118-CN is a high-speed silicon gate CMOS device with pin compatibility with Low-power Schottky TTL (LSTTL). The device conforms to JEDEC standard no. 7A. The "595" is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted in on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7') for cascading. It also provides an asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Whenever the output enable input (OE) is LOW, the data in the storage register appears at the outputs.

Applications

• Serial-to-parallel data conversion
• Remote-controlled hold register

Key features

• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100MHz (typical) shift output frequency
• Output drive: parallel outputs; bus driver
• Output drive: serial output; standard