AD4081BBCZ

The AD4081 is a high speed, low noise, low distortion, 20-bit easy drive successive approximation register ADC. The device maintains high performance at signal frequencies exceeding 1 MHz, with a signal-to-noise and distortion ratio greater than 90 dBFS, making it suitable for a wide range of precision wideband data acquisition applications. For applications that do not require the lowest latency of the AD4081, oversampling combined with integrated digital filtering and decimation can simplify the input antialiasing filter design, reducing noise and lowering the output data rate. The easy drive feature of the AD4081 reduces signal chain complexity and power consumption while increasing channel density and flexibility in companion component selection. The input structure is designed to minimize any input-related signal currents, thereby reducing converter-induced settling artifacts. The continuous acquisition architecture allows settling throughout the entire conversion cycle, easing the settling and bandwidth requirements on the ADC driver compared to other high speed data converters. The AD4081 integrates multiple elements that simplify data converter integration: a low drift reference voltage buffer, LDOs for generating the ADC core and digital interface supply rails, and a 16K result data FIFO that significantly reduces the digital host burden. In addition, critical power supply and reference decoupling capacitors are integrated within the package to ensure optimum performance, simplify PCB layout, and reduce the overall solution footprint.

Applications

• Digital imaging
• Cell analysis
• Spectroscopy
• Automated test equipment
• High-speed data acquisition

Key features

• High performance: 20MSPS throughput, 77.50ns conversion latency; typical INL ±4ppm, max ±8ppm; dynamic range 94.6dBFS
• SNR/THD: at fIN = 1kHz, typical 94dB / typical -117.3dB; at fIN = 1MHz, typical 93.7dB / typical -103.7dB
• Noise spectral density: -164.6dBFS/Hz
• 20-bit resolution, no missing codes
• Low power: typical 68.6mW at 20MSPS with -0.5dBFS sine wave input
• Easy to drive, fully differential input: 6V peak-to-peak differential input range
• Continuous signal acquisition
• Linearized input current: 5μA/MSPS
• Integrated low-drift reference voltage buffer and decoupling
• Integrated VCM generation
• Digital features and data interface: conversion result FIFO depth 16K samples; digital averaging filter with decimation ratio up to 2^10
• SPI configuration
• Configurable data interface: single-channel DDR serial LVDS at 400Mbps per channel; dual-channel DDR serial LVDS at 200Mbps per channel; single/quad-channel SPI data interface
• Package: 49-ball, 5mm×5mm chip-scale BGA, 0.65mm pitch
• Integrated power supply decoupling capacitors
• Operating temperature range: -40℃ to +85℃