AD9233BCPZ-125

The AD9233 is a single-chip, 12-bit, 80 MSPS/105 MSPS/125 MSPS ADC operating from a 1.8 V single supply, with an integrated high-performance SHA and on-chip voltage reference. It employs a multistage differential pipelined architecture with integrated output error correction logic, delivering 12-bit accuracy at 125 MSPS data rates with guaranteed no missing codes over the full operating temperature range. The wide-bandwidth, true differential SHA allows users to select from a variety of input ranges and bias configurations, including single-ended applications. The device is suited for multiplexed systems where full-scale input signals switch between successive channels, as well as single-channel input sampling at frequencies well beyond the Nyquist rate. Compared to previous ADCs, the AD9233 offers reduced power consumption and cost, making it suitable for communications, imaging, and medical ultrasound applications. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in clock duty cycle while maintaining excellent overall ADC performance. Digital output data formats include offset binary, Gray code, or two's complement. A data output clock (DCO) ensures correct latch timing for the receiving logic. The AD9233 is available in a 48-lead LFCSP and is rated for the -40°C to +85°C industrial temperature range.

Applications

• Ultrasonic equipment
• IF-sampling communication receivers
• IS-95, CDMA-One, IMT-2000
• Battery-powered instrumentation
• Handheld oscilloscopes
• Low-cost digital oscilloscopes

Key features

• 1.8 V analog supply
• 1.8 V to 3.3 V output levels
• SNR: 69.5 dBc (70.5 dBFS, to 70 MHz input)
• SFDR: 85 dBc (to 70 MHz input)
• Low power: 395 mW @125 MSPS
• Differential input, 650 MHz bandwidth
• On-chip voltage reference and SHA
• DNL: ±0.15 LSB
• Flexible analog input range: 1 V p-p to 2 V p-p
• Data format: offset binary, Gray code, or twos complement
• Clock duty cycle stabilizer
• Data output clock
• Serial port control with built-in optional digital test pattern generation and programmable clock-to-data alignment
• The AD9233 operates from a 1.8 V supply, while the digital output drivers use a separate supply to accommodate 1.8 V to 3.3 V logic
• Patented SHA input maintains excellent performance at input frequencies up to 225 MHz
• Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths
• Standard serial port interface supports various product features and functions, including data formatting (offset binary, twos complement, or Gray code), clock DCS enable, power-down mode, and voltage reference mode
• The AD9233 is pin-compatible with the AD9246, enabling easy upgrade from 12-bit to 14-bit products