Varnitronics
ADI

AD9268BCPZ-80

LFCSP-64 Analog to Digital Converters (ADC)

LFCSP-64RoHSActive

16-Bit, 80/105/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Manufacturer
ADI
Manufacturer part #
AD9268BCPZ-80
Store part #
C2903965
Package / case
LFCSP-64
Packaging
Tray
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

95 in stock

#C2903965

Stock & price checked 2 days ago

QuantityUnit pricePack price
1+₹10,844.94₹10,844.94
30+₹10,344.22₹3,10,326.60

1 × ₹10,844.94

₹10,844.94

excl. GST

₹12,797.03 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 260 per tray

AD9268BCPZ-80

₹10,844.94 for 1 + GST

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Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tray
Standard pack
260 / Tray
Sold per
Piece
Minimum order
1
Unit weight
1 g

Overview

The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of -40°C to +85°C.

Applications

  • Communications Diversity radio systems
  • Multimode digital receivers (3G)
  • GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems
  • Smart antenna systems
  • General-purpose software radios
  • Broadband data applications
  • Ultrasound equipment

Key features

  • SNR = 78.2 dBFS @ 70 MHz and 125 MSPS
  • SFDR = 88 dBc @ 70 MHz and 125 MSPS
  • Low power: 750 mW @ 125 MSPS
  • 1.8 V analog supply operation
  • 1.8 V CMOS or LVDS output supply
  • Integer 1-to-8 input clock divider
  • IF sampling frequencies to 300 MHz
  • −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
  • Optional on-chip dither
  • Programmable internal ADC voltage reference
  • Integrated ADC sample-and-hold inputs
  • Flexible analog input range: 1 V p-p to 2 V p-p
  • Differential analog inputs with 650 MHz bandwidth
  • ADC clock duty cycle stabilizer
  • 95 dB channel isolation/crosstalk
  • Serial port control
  • User-configurable, built-in self-test (BIST) capability
  • Energy-saving power-down modes

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