AD9648BCPZ-105

The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock

Applications

• Communications
• Diversity radio systems
• Multimode digital receivers
• GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TO-SCDMA
• I/Q demodulation systems
• Smart antenna systems
• Broadband data applications
• Battery-powered instruments
• Hand held scope meters
• Portable medical imaging
• Ultrasound
• Radar/LIDAR

Key features

• 1.8 V analog supply operation
• 1.8 V CMOS or LVDS outputs
• SNR = 74.5 dBFS @ 70 MHz
• SFDR = 91 dBc @ 70 MHz
• Low power: 106 mW/channel @ 125 MSPS
• Differential analog input with 650 MHz bandwidth
• IF sampling frequencies to 200 MHz
• On-chip voltage reference and sample-and-hold circuit
• 2 V p-p differential analog input
• DNL = ±0.5 LSB
• Serial port control options
• Offset binary, gray code, or twos complement data format
• Optional clock duty cycle stabilizer
• Integer 1-to-8 input clock divider
• Data output multiplex option
• Built-in selectable digital test pattern generation
• Energy-saving power-down modes
• Data clock out with programmable clock and data alignment