ADC32RF80IRRHR

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a series of 14-bit, 3GSPS dual-channel telecommunications receivers and feedback devices that support RF sampling with input frequencies up to 4GHz and above. The ADC32RF8x series is designed to achieve high signal-to-noise ratio (SNR), featuring a noise spectral density of –155dBFS/Hz and dynamic range over a wide input frequency range while providing channel isolation. The buffered analog inputs are equipped with on-chip termination resistors, which provide a uniform input impedance over a wide frequency range and minimize the sample-and-hold glitch energy. Each channel can be connected to a dual-band digital downconverter (DDC), and each DDC can be connected to up to three independent 16-bit numerically controlled oscillators (NCOs) for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and an alarm function to support external automatic gain control (AGC) algorithms. The ADC32RF8x supports the JESD204B serial interface with subclass 1 deterministic latency, with a data rate of up to 12.5Gbps and up to four lanes per ADC. The device is packaged in a 72-pin VQFN package (10mm × 10mm) and supports the industrial temperature range (-40°C to +85°C).

Applications

• Multi-carrier GSM cellular infrastructure base station telecom receivers
• Digital predistortion (DPD) observation receivers
• Backhaul receivers
• RF repeaters and distributed antenna systems

Key features

• 14-bit dual-channel 3GSPS ADC
• Noise floor: –155dBFS/Hz
• RF input frequency support up to 4.0GHz
• Aperture jitter: 90fS
• Channel isolation: 95dB at fIN = 1.8GHz
• Spectral performance (fIN = 900MHz, –2dBFS):
• SNR: 60.1dBFS
• SFDR: 66dBc HD2, HD3
• SFDR: 76dBc worst spur
• Spectral performance (fIN = 1.85GHz, –2dBFS):
• SNR: 58.9dBFS
• SFDR: 67dBc HD2, HD3
• SFDR: 76dBc worst spur
• On-chip digital downconverter:
• Up to 4 DDCs (dual-band mode)
• Up to 3 independent NCOs per DDC
• On-chip input clamp with overvoltage protection
• Programmable on-chip power detector with alarm pin for AGC support
• On-chip dither
• On-chip input termination resistor
• Full-scale input: 1.35V VPP
• Multi-chip synchronization support
• JESD204B interface:
• Subclass 1-based deterministic latency
• 4 lanes per channel at 12.5Gbps
• Power dissipation: 3.2W/channel at 3.0GSPS
• 72-pin VQFN package (10mm×10mm)