ADC3548IRTDT

The ADC3548 and ADC3549 (ADC354x) are 14-bit, single-channel analog-to-digital converters (ADCs) with sample rates of 250 MSPS and 500 MSPS, respectively. Designed for high SNR performance, the device delivers a noise spectral density as low as -158.5 dBFS/Hz. This power-efficient ADC architecture consumes 435 mW at 500 MSPS with power scaling as the sample rate decreases, reaching 369 mW at 250 MSPS. The ADC354x integrates a four-band digital down converter (DDC) supporting decimation from 2× wide to 32768× narrow. The DDC features a 48-bit NCO with support for phase-coherent and phase-continuous frequency hopping. The ADC354x offers a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit-wide parallel SDR or DDR LVDS interface. When decimation is enabled, output data is transmitted over a serial LVDS interface, reducing the number of required lanes as the decimation rate increases. At high decimation rates, output resolution can be extended to 32 bits.

Applications

• Software Defined Radio
• Spectrum Analyzer
• Spectroscopy
• Power Amplifier Linearization
• Communications Infrastructure

Key features

• 14-bit single-channel ADC, supporting 250MSPS and 500MSPS sample rates
• Noise spectral density: -158.5dBFS/Hz
• Thermal noise: 74.5dBFS
• Single-core (non-interleaved) ADC architecture
• Power consumption: 435mW at 500MSPS, 369mW at 250MSPS
• Aperture jitter: 75fs
• Buffered analog input with programmable 100Ω and 200Ω termination
• Input full-scale: 2 Vpp
• -3dB full-power input bandwidth: 1.4GHz
• Spectral performance at fIN = 70MHz, -1dBFS: SNR 73.8dBFS, HD2/HD3 SFDR 82dBc, worst-spur SFDR 94dBFS
• Supports up to four independent digital downconverters (DDC)
• Complex and real decimation support
• Decimation range: 2x, 4x to 32768x
• 48-bit NCO with phase-coherent frequency hopping
• DDR/serial LVDS interface support
• 16-bit parallel SDR/DDR LVDS in DDC bypass mode
• Serial LVDS output in decimation mode
• 32-bit output option at high decimation rates