ADC3642IRSBR

The ADC364x series is a dual-channel high-speed analog-to-digital converter (ADC) with low noise, ultra-low power consumption, 14-bit resolution, and sampling rates ranging from 10 MSPS to 65 MSPS. It can achieve low power consumption, with a noise spectral density of –155 dBFS/Hz, and offers excellent linearity and dynamic range. It can achieve excellent DC accuracy and support intermediate frequency sampling. The high-speed control loop benefits from the low latency of only one clock. The power consumption is only 72 mW per channel at 65 MSPS, and the power consumption decreases rapidly as the sampling rate decreases. It uses a DDR or serial CMOS interface to output data, providing an ultra-low-power digital interface and flexibly minimizing the number of digital interconnections. It belongs to a pin-to-pin compatible series with different speed grades and supports an industrial operating temperature range of –40°C to +105°C.

Applications

• High-speed data acquisition
• Industrial monitoring
• Thermal imaging
• Imaging & sonar
• Software defined radio
• Power quality
• Communications infrastructure
• High-speed control loops
• Instrumentation
• Smart grid
• Spectrum analysis
• Radar
• Source measure unit (SMU)
• GPS receivers
• Sonar
• Substation automation

Key features

• Dual-channel 14-bit 10/25/65 MSPS ADC
• Noise floor: –155 dBFS/Hz
• Ultra-low power with optimized power scaling: 29mW/channel (10MSPS) to 72mW/channel (65MSPS)
• Latency: 1 clock cycle
• 14-bit, no missing codes
• INL: ±0.6LSB; DNL: ±0.2LSB
• Reference: external or internal
• Industrial temperature range: -40°C to +105°C
• On-chip digital filter (optional)
• 2×, 4×, 8×, 16×, 32× decimation rates
• 32-bit NCO
• DDR and serial CMOS interface
• Small footprint: 40-pin VQFN (5mm×5mm) package
• 1.8V single supply
• Spectral performance (fIN = 5MHz):
• SNR: 79.0 dBFS
• SFDR: 93dBc HD2, HD3
• SFDR: 101dBFS worst spur
• Spectral performance (fIN = 64MHz):
• SNR: 74.0dBFS
• SFDR: 84dBc HD2, HD3
• SFDR: 90dBFS worst spur