ADM1060ARUZ

The ADM1060 is a programmable supervisory/sequencing device that offers a single chip solution for multiple power supply fault detection and sequencing in communications systems. In central offices, servers, and other infrastructure systems, a common backplane dc supply is reduced to multiple board supplies using dc-to-dc converters. These multiple supplies are used to power different sections of the board, such as 3.3 V logic circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There is usually a requirement that certain sections power up before others; for example, a DSP core may need to power up before the DSP I/O, or vice versa, to avoid damage, miscommunication, or latch-up. The ADM1060 facilitates this, providing supply fault detection and sequencing/combinatorial logic for up to seven independent supplies. The seven supply fault detectors consist of one high voltage detector (up to +14.4 V), two bipolar voltage detectors (up to +6 V or down to -6 V), and four positive low voltage detectors (up to +6 V). All of the detectors can be programmed to detect undervoltage, overvoltage, or out-ofwindow (undervoltage or overvoltage) conditions. The inputs to these supply fault detectors are via the VH (high voltage) pin, VBn (positive or negative) pins, and VPn (positive only) pins. Either the VH supply or one of the VPn supplies is used to power the ADM1060 (whichever is highest). This ensures that in the event of a supply failure, the ADM1060 is kept alive for as long as possible, thus enabling a reliable fault flag to be asserted and the system to be powered down in an ordered fashion. Other inputs to the ADM1060 include a watchdog detector (WDI) and four general-purpose inputs (GPIn). The watchdog detector can be used to monitor a processor clock. If the clock does not toggle (transition from low to high or from high to low) within a programmable timeout period (up to 18 sec.), a fail flag will assert. The four general-purpose inputs can be configured as logic buffers or to detect positive/negative edges and to generate a logic pulse or level from those edges. Thus, the user can input control signals from other parts of the system (e.g., RESET or POWER_GOOD) to gate the sequencing of the supplies supervised by the ADM1060. The ADM1060 features nine programmable driver outputs (PDOs). All nine outputs can be configured to be logic outputs, which can provide multiple functions for the end user such as RESET generation, POWER_GOOD status, enabling of LDOs, and watchdog timeout assertion. PDOs 1 to 4 have the added feature of being able to provide an internally charge-pumped high voltage for use as the gate drive of an external N-channel FET that could be placed in the path of one of the supplies being supervised. All of the inputs and outputs described previously are controlled by the programmable logic block array (PLBA). This is the logic core of the ADM1060. It is comprised of nine macrocells, one for each PDO. These macrocells are essentially just wide AND gates. Any/all of the inputs can be used as an input to these macrocells. The output of a macrocell can also be used as an input to any macrocell other than itself (an input to itself would result in a nonterminating loop). The PLBA outputs control the PDOs of the ADM1060 via delay blocks, where a delay of 0 ms to 500 ms can be programmed.

Applications

• Central office systems
• Servers
• Infrastructure network boards
• High density, multivoltage system cards

Key features

• Faults detected on 7 independent supplies
• 1 high voltage supply (2 V to 14.4 V)
• 4 positive voltage only supplies (2 V to 6 V)
• 2 positive/negative voltage supplies (+2 V to +6 V and -2 V to –6 V)
• Watchdog detector input—timeout delay programmable from 2800 ms to 12.8 sec
• 4 general-purpose logic inputs
• Programmable logic block—combinatorial and sequencing logic control of all inputs and outputs
• 9 programmable output drivers: Open collector (external resistor required) Open collector with internal pull-up to VDD Fast internal pull-up to Voo Open collector with internal pull-up to VPn Fast internal pull-up to VPn Internally charge-pumped high drive (for use with external N-channel FETs—PDOs 1 to 4 only)
• EEPROM—256 bytes of user EEPROM
• Industry-standard 2-wire bus interface (SMBus)
• Guaranteed PDO low with VPn, VH = 1 V