ADP1762ACPZ-1.3-R7

The ADP1762 is a low noise, low dropout (LDO) linear regulator. It is designed to operate from a single input supply with an input voltage as low as 1.10 V, without the requirement of an external bias supply, to increase efficiency and provide up to 2 A of output current. The low 62 mV typical dropout voltage at a 2 A load allows the ADP1762 to operate with a small headroom while maintaining regulation and providing better efficiency.

Applications

• Regulation to noise sensitive applications such as radio frequency (RF) transceivers, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits, phase-locked loops (PLLs), voltage controlled oscillators (VCOs) and clocking integrated circuits
• Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies
• Medical and healthcare
• Industrial and instrumentation

Key features

• 2 A maximum output current
• Low input voltage supply range VIN = 1.10 V to 1.98 V, no external bias supply required
• Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
• Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
• Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
• Noise spectral density 4 nV/√Hz at 10 kHz, 3 nV/√Hz at 100 kHz
• Low dropout voltage: 62 mV typical at 2 A load
• Operating supply current: 4.5 mA typical at no load
• ±1.5% fixed output voltage accuracy over line, load, and temperature
• Excellent power supply rejection ratio (PSRR) performance: 62 dB typical at 10 kHz at 2 A load, 46 dB typical at 100 kHz at 2 A load
• Excellent load/line transient response
• Soft start to reduce inrush current
• Optimized for small 10 μF ceramic capacitors
• Current-limit and thermal overload protection
• Power-good indicator
• Precision enable
• 16-lead, 3 mm × 3 mm LFCSP package
• AEC-Q100 qualified for automotive applications