DS90C401MX/NOPB

DS90C401 is a dual-driver device optimized for high data rate and low power applications. Used in conjunction with DS90C402, it provides a two-chip solution for dual high-speed point-to-point interfaces. DS90C401 is a current-mode driver that maintains low power consumption even at high frequencies. In addition, short-circuit fault current is minimized. The device is offered in an 8-pin small outline package. The differential driver output swing is low, enabling low EMI, with a typical value of 340 mV. These devices incorporate limited ESD protection; during storage or handling, pins should be shorted together or the device placed in conductive foam to prevent electrostatic damage to MOS gates. LVDS drivers and receivers are primarily used in simple point-to-point configurations, which provide a clean signal environment for the driver's fast edge rates. The receiver connects to the driver through a balanced medium, which may be standard twisted-pair cable, parallel-pair cable, or simply PCB traces. The characteristic impedance of the medium is typically in the 100Ω range; a 100Ω termination resistor should be selected to match the medium and placed as close as possible to the receiver input pins. The termination resistor converts the current from the driver output into a voltage detectable by the receiver. Other topologies such as multi-receiver configurations are also achievable, but the effects of intermediate connectors, cable stubs, other impedance discontinuities, ground offsets, noise margin limitations, and total termination load must be considered. The DS90C401 differential line driver uses a balanced current source design. In general, current-mode drivers have high output impedance, providing constant current over a range of loads. The current switches through the load in one direction to produce one logic state, and in the other direction to produce the other logic state, with a typical output current of 3.4 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. Current mode requires resistive termination to terminate the signal and complete the loop; AC termination or unterminated configurations are not permitted. The 3.4 mA loop current develops a 340 mV differential voltage across the 100Ω termination resistor for detection by the receiver.

Applications

• High-speed point-to-point interface
• Multi-receiver configuration interface

Key features

• Ultra Low Power Dissipation
• Operates Above 155.5 Mbps
• Standard TIA/EIA - 644
• 8 Lead SOIC Package Saves Space
• Low Differential Output Swing typical 340 mV