HTC74HC165

The HTC74HC165 is an 8-bit parallel-load shift register that shifts data toward the serial (QH) output on each clock pulse. Parallel input access to each stage is provided through eight individual direct data (A–H) inputs, which are enabled when the shift/load (SH/LD) input is LOW. The HTC74HC165 also features a clock inhibit (CLK INH) function and complementary serial (QH) outputs. When SH/LD is held HIGH and CLK INH is held LOW, clocking is accomplished by a LOW-to-HIGH transition on the clock (CLK) input. The CLK and CLK INH functions are interchangeable. Since a LOW-to-HIGH transition on either CLK or CLK INH will clock the device, CLK INH should only be changed to HIGH while CLK is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. When SH/LD is LOW, the parallel inputs of the register are enabled independently of the levels on CLK, CLK INH, or the serial (SER) input.

Key features

• Complementary outputs
• Direct overriding load (data) input
• Gated clock input
• Parallel-to-serial data conversion