NCV308SN500T1G

The NCV308 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VIT or the Manual Reset input (MR) is driven low. The RESET output remains asserted for a programmable delay time after both MR and SENSE voltages return above the respective thresholds. A broad range of voltage threshold and reset delay time options are available, allowing NCV308 series to be used in a wide range of applications. Reset threshold voltages can be factory−set from 1.67 V to 4.65 V while the NCV308SNADJ can be used for any voltage above 0.405 V using an external resistor divider. The RESET output is typically connected to the RESET control pin of a microprocessor. For Open−Drain output versions, a pull−up resistor must be used to hold this line high when RESET is not asserted. The RESET output is active once VDD is over VDD(min), this voltage is much lower than most microprocessors’ functional voltage range. RESET remains high as long as SENSE is above its threshold (VIT) and the Manual Reset input (MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted. The SENSE input should be connected to the monitored voltage directly. If the voltage on this pin drops below VIT, then RESET is asserted. The comparator has a built−in hysteresis to prevent erratic reset operation. It is good practice to put a 1 nF to 10 nF bypass capacitor on the SENSE input to reduce its sensitivity to transients and layout parasitic. Once MR is again logic high and SENSE is above (VIT + VHYS), the RESET pin goes to a high impedance state after delay time (tD). The open−drain structure of RESET is capable to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 5.5 V). The pull−up resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.

Applications

• DSP or Microcontroller Applications
• Notebook/Desktop Computers
• PDAs/Hand−Held Products
• Portable/Battery−Powered Products
• FPGA/ASIC Applications

Key features

• Wide Supply Voltage Range 1.6 to 5.5 V
• Very Low Quiescent Current 1.6 μA
• Fixed Threshold Voltage Versions for Standard Voltage Rails Including 1.8 V, 3.3 V, 5.0 V
• Adjustable Version with Low Threshold Voltage 0.405 V (min)
• High Threshold Voltage Accuracy: 0.15% typ
• Support Manual Reset Input (MR)
• Open−Drain RESET Output (Push−pull Output upon Request)
• Flexible Delay Time Programmability: 1.25 ms to 10 s
• Temperature Range: -40°C to +125°C
• Small TSOP−6 Pb−Free Package
• NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Grade 1 Qualified and PPAP Capable
• These are Pb−Free Devices