SN74AVC16244DGGR

This 16-bit buffer/driver operates from 1.2V to 3.6V VCC and is optimized for 1.65V to 3.6V VCC applications. The SN74AVC16244 is specifically designed to improve performance and integration density for three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be configured as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer, providing noninverting outputs and symmetric active-low output enable (OE) inputs. The device incorporates a dynamic output control (DOC) circuit that, during signal transitions, first reduces output impedance to effectively drive the load, then increases impedance to reduce noise. At the onset of a signal transition, the DOC circuit provides maximum dynamic drive equivalent to that of high-drive standard output devices. The device is fully characterized for partial-power-down applications using Ioff. The Ioff circuit disables the outputs, preventing damaging backflow current when the device is powered down. To maintain a high-impedance state during power-up or power-down, OE should be connected to VCC through a pullup resistor, with the minimum resistance value determined by the current-sinking capability of the driver.

Applications

• Tri-state memory address driver
• Clock driver
• Bus-oriented receiver
• Bus-oriented transmitter

Key features

• Part of the Texas Instruments Widebus™ family
• Integrated DOC™ (Dynamic Output Control) circuitry dynamically adjusts output impedance to reduce noise without sacrificing speed
• Maximum propagation delay less than 2 ns at 2.5V and 3.3V VCC
• Dynamic drive capability equivalent to standard outputs, with IOH and IOL of ±24 mA at 2.5V VCC
• Input/output overvoltage tolerance for mixed-voltage data communication
• Ioff supports partial power-down operation
• Latch-up performance exceeds the 100 mA requirement of JESD 78 Class II
• ESD protection performance exceeds JESD 22 requirements
• Meets 2000-V Human Body Model (A114-A)
• Meets 200-V Machine Model (A115-A)