SN74AVC16827DGGR

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. This 20-bit noninverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE(overline)) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16827 is characterized for operation from -40℃ to 85℃.

Applications

• Mixed-voltage mode data communications

Key features

• Member of the Texas Instruments Widebus™ Family
• EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
• DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
• Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC
• Dynamic Drive Capability Is Equivalent to Standard Outputs With I₀ₕ and I₀ₗ of ±24 mA at 2.5-V VCC
• Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages