SN74LV244ADWR

These octal buffers/line drivers are designed for 2- V to 5.5- V VCC operation. The 'LV244A devices are designed specifically to improve both the performance and density of 3- state memory address drivers, clock drivers, and bus- oriented receivers and transmitters. These devices are organized as two 4- bit line drivers with separate output- enable (OE(overline)) inputs. When OE(overline) is low, the device passes data from the A inputs to the Y outputs. When OE(overline) is high, the outputs are in the high- impedance state. To ensure the high- impedance state during power up or power down, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current- sinking capability of the driver. These devices are fully specified for partial- power- down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Applications

• Three-state memory address driver
• Clock driver
• Bus-oriented receivers and transmitters

Key features

• 2-V to 5.5-V VCC Operation
• Max tpd of 6.5 ns at 5 V
• Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
• Typical VOHV (Output VOH Undershoot) >2.3V at VCC = 3.3V, TA = 25℃
• Support Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)