SN74LV244ATRGYR

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE(overline)) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE(overline) is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE(overline) shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Applications

• Three-state memory address driver
• Clock driver
• Bus-oriented receivers and transmitters

Key features

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V Vcc Operation
• Typical tpd = 5.4 ns at 5V
• Typical VoLP (Output Ground Bounce) < 0.8V at VCC = 50, TA = 25℃
• Typical VoHV (Output VoH Undershoot) > 2.3 V at Vcc = 5 V, TA = 25℃
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)