SN74LVC646ADBR

The SN54LVC646A octal bus transceivers and registers are designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC646A octal bus transceivers and registers are designed for 1.65-V to 3.6-V VCC operation. These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexing data from the input buses or internal registers. Data on the A bus or B bus is latched into the registers on the low-to-high transition of the respective clock (CLKAB or CLKBA) input. The output enable (OE) and direction control (DIR) inputs control the transceiver functions. In the transceiver mode, data present on the high-impedance port is stored in one or both registers. The select control (SAB and SBA) inputs can multiplex stored data and real-time (transparent mode) data. When OE is low, DIR determines which bus receives data. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When the output function is disabled, the input function remains enabled and can be used for storing and transferring data. Only one of the two buses, A or B, can be driven at a time. The inputs can be driven by 3.3-V or 5-V devices. This feature allows these devices to be used as translators in mixed 3.3-V/5-V system environments. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuit disables the outputs, preventing damaging backflow current when the device is powered down. To ensure the high-impedance state during power-up or power-down, OE should be connected to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Key features

• Operating voltage range: 1.65 V to 3.6 V
• Inputs accept voltages up to 5.5 V
• Maximum tpd of 7.4 ns at 3.3 V
• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25 ℃
• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25 ℃
• Mixed-mode signal operation on all ports (5 V input/output voltages at VCC = 3.3 V)
• Ioff supports partial power-down mode operation
• Latch-up performance exceeds 250 mA per JESD 17
• ESD protection exceeds JESD 22:
• 2000 V Human Body Model (A114-A)
• 200 V Machine Model (A115-A)
• 1000 V Charged Device Model (C101)