SN74LVTH652DW

These bus transceivers and registers are designed for low-voltage operation at 3.3-V VCC while providing TTL interface capability to 5-V system environments. The LVTH652 device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged to support multiplexed data transfer either directly from the data bus or from the internal storage registers. The output-enable (OEAB and OEBA) inputs control the transceiver function, and the select-control (SAB and SBA) inputs select whether real-time or stored data is transferred. The circuitry used for the select control eliminates the typical decoding glitches that occur in multiplexers during transitions between real-time and stored data. A low input selects real-time data; a high input selects stored data. Data on the A bus or B bus (or both) can be stored in the internal D-type flip-flops on the low-to-high transition of the corresponding clock (CLKAB or CLKBA) input, independent of the select-control or enable-control pins. When SAB and SBA are in the real-time transfer mode, data can be stored without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore, when all other data sources on both buses are in the high-impedance state, each bus retains its last state. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 V and 1.5 V, the device is in the high-impedance state during power-up or power-down. However, to ensure the high-impedance state above 1.5 V, OE should be connected to VCC through a pullup resistor and OE should be connected to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/sourcing capability of the driver. The device is fully characterized for hot-insertion applications using the Ioff and power-up three-state features. The Ioff circuit disables the outputs, preventing damaging backflow current when the device is powered down. The power-up three-state circuit places the outputs in the high-impedance state during power-up and power-down, preventing driver conflicts. The data output function can be enabled or disabled by various combinations of levels on OEAB or OEBA. The data input function is always enabled — that is, data at the bus terminals is stored on every low-to-high transition of the clock inputs. When the select control is low, the clocks can be applied simultaneously; when the select control is high, the clocks must be staggered to load both registers.

Applications

• Hot-plug applications

Key features

• Mixed-mode signal operation support (5-V I/O voltage with 3.3-V VCC)
• Unregulated battery operation down to 2.7 V
• Bus-hold on data inputs — no external pull-up/pull-down resistors required
• Latch-up performance exceeds 500 mA per JESD 17
• ESD protection exceeds JESD 22
• 2000-V Human Body Model (A114-A) compliant
• 200-V Machine Model (A115-A) compliant
• Ioff and power-up 3-state support for hot-plug applications