STM6510SCACDG6F

The STM65xx series in the Smart Reset product family features a highly useful function using an extended SmartReset input delay (tSRC) to ensure that brief reset button closures do not trigger a system reset. Once a valid Smart Reset input level and startup delay are met, the device generates an output reset pulse with a user-programmable timeout period (tREC). A typical application schematic shows that dual Smart Reset inputs can also be connected to application interrupts to control the interrupt pin and hard reset functions. If the button is closed for a brief period, the processor is only interrupted. If the system still fails to respond normally, holding the button down for the extended startup time (tSRC) triggers a hard reset of the processor via the reset output. The Smart Reset function effectively enhances system stability. The STM65xx series Smart Reset products integrate a low-current microprocessor reset circuit, targeting applications such as MP3 players, portable navigation devices, or mobile phones — any application requiring a delayed reset button response for improved system stability. The STM65xx series offers single or dual Smart Reset inputs (SRx). The delayed Smart Reset startup time (tSRC) option is adjustable by adding an external capacitor on the SRC pin or through tri-state logic selection. The delayed startup period ignores switch closures shorter than tSRC, thereby preventing unwanted resets. The STM65xx series provides active-low (active-high optional) open-drain reset (RST) outputs, with or without internal pull-up resistors, or push-pull outputs; products are available with or without power-on reset functionality. Some products also feature a low-voltage monitoring function: when the monitored voltage VCC falls below a specified threshold, the reset output is simultaneously activated. After VCC rises above the specified threshold, the reset output remains asserted for the duration of the reset timeout period (tREC). The STM6510 features two combined Smart Reset input pins (SR0 and SR1) with a Smart Reset startup delay (tSRC) programmed by an external capacitor on the SRC pin. Another feature of the STM6510 is that the output reset pulse duration tREC is adjustable by adding an external capacitor (CtREC). In addition, VCC is monitored: if it falls below the VRST threshold, the reset output becomes active and remains asserted as long as VCC stays below the VRST threshold, followed by the reset pulse duration tREC.

Applications

• Mobile phones, smartphones
• E-readers
• MP3 players
• Gaming consoles
• Portable navigation devices

Key features

• Dual Smart Reset button inputs with capacitor-adjustable extended reset startup delay (tSRC)
• Capacitor-adjustable reset pulse duration (tREC)
• Power-on reset – RST active-low, open-drain output
• Factory-programmed threshold, monitors VCC in the range of 1.575 to 4.625V (typical)
• Operating voltage 1.0V (active-low output valid) to 5.5V
• Low supply current (1.4μA)
• Operating temperature: Industrial grade -40°C to +85°C
• TDFN8 package: 2mm×2mm×0.75mm
• RoHS compliant