TLC1549CP

The TLC1549C, TLC1549I, and TLC1549M are 10-bit switched-capacitor successive-approximation ADCs. These devices feature two digital inputs and one three-state output (CS, I/O CLOCK, and DATA OUT), providing a three-wire interface for connection to a host processor serial port. The sample-and-hold function is automatic. The on-chip converter incorporates a differential high-impedance reference input, facilitating ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. The switched-capacitor design allows low-error conversions across the full operating free-air temperature range. The TLC1549C operates from 0°C to 70°C, and the TLC1549I operates from -40°C to 85°C. When CS is inactive (high), the I/O CLOCK is initially disabled and DATA OUT is in a high-impedance state. When the serial port asserts CS active (low), the conversion sequence begins, the I/O CLOCK is enabled, and DATA OUT exits the high-impedance state. The serial port then provides a clock sequence to the I/O CLOCK and receives the previous conversion result from DATA OUT. The I/O CLOCK accepts an input sequence of 10 to 16 clocks from the host serial port. The first 10 I/O clocks provide the control timing for analog input sampling. The device supports six basic serial interface timing modes, determined by the I/O CLOCK speed and the CS operating state. All modes require a minimum interval of 21 µs after the falling edge of the tenth I/O CLOCK before a new transfer sequence can begin. During serial I/O CLOCK data transfer, CS must remain active (low) to enable the I/O CLOCK. When CS toggles between data transfers (modes 1, 3, and 5), a state transition is recognized as valid only after the level has been stable for at least 1.425 µs. If a transfer exceeds ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within 9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device may lose synchronization with the host serial port, requiring a CS toggle to restore normal operation. When the serial I/O CLOCK data transfer completes within 21 µs after the falling edge of the tenth I/O CLOCK, the TLC1549 operates in fast mode; ten-clock serial transfers can only operate in fast mode.

Key features

• 10-bit resolution ADC
• Built-in sample-and-hold
• On-chip system clock
• CMOS process