TLV1504IPWR

The TLV1508 and TLV1504 are a family of high performance, 10-bit low power, 3.86 μs, CMOS analog-to-digital converters (ADC) which operate from a single 2.7-V to 5.5-V power supply. These devices have three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a TMS320 v DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame. In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular among high-performance signal processors. The TLV1508 and TLV1504 are designed to operate with very low power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down modes and programmable conversion speeds. The conversion clock (OsC) and reference are built-in. The converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 μs when a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional external reference can also be used to achieve maximum flexibility. The TLV1504l and the TLV1508l are characterized for operation from -40°C to 85°C The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. The TLV1504/48 uses a 10-bit successive approximation ADC utiling a charge redistribution DAC. The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. Input data is binary. All trailing blanks can be filled with zeros. The output data format is binary (unipolar straight binary). Zero scale code = 000h, Vcode = VREFM Full scale code = 3FFh, Vcode = VREFP - 1LSB

Key features

• Maximum Throughput 200-KSPS
• Built-in Reference, Conversion Clock and 8x FIFO
• Differential/Integral Nonlinearity Error: ±1 LSB
• Signal-to-Noise and Distortion Ratio: 59 dB, fi = 12-kHz
• Spurious Free Dynamic Range: 72 dB, ti = 12-kHz
• SPI (CPOL = 0, CPHA = 0); /DSP-Compatible Serial Interfaces With SCLK up to 20-MHz
• Single Wide Range Supply 2.7 Vdc to 5.5 Vdc
• Analog Input Range 0-V to Supply Voltage, With 500kHz BW
• Hardware Controlled and Programmable Sampling Period
• Low Operating Current (1.0-mA at 3.3-V, 1.1-mA at 5.5-V With External Ref)
• Power Down: Software/Hardware Power-Down Mode (0.1 μA Max, Ext Ref), Autopower-Down Mode (1 μA Ext Ref)
• Programmable Auto-Channel Sweep
• Pin Compatible 12-Bit Upgrades Available (TLV2544, TLV2548)