ADC09QJ800AAV

The ADC09xJ800 is a series of 9-bit, 800MSPS four-channel/two-channel/single-channel analog-to-digital converters (ADCs) with low power consumption, high sampling rate, and 12-bit resolution. These features make the ADC09xJ800 well-suited for various multi-channel communication and test systems. The 6GHz full-power input bandwidth (-3dB) also supports direct RF sampling in the L and S bands. It includes many clock functions to relax system hardware requirements, such as an internal phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) for generating the sampling clock. Four clock outputs are provided to time the logic and serializers/deserializers of FPGAs or ASICs. Timestamp inputs and outputs are provided for pulse systems. The JESD204C serial interface reduces the system size by minimizing the amount of printed circuit board (PCB) wiring. The interface mode supports 2 to 8 channels (dual-channel and quad-channel devices) or 1 to 4 channels (single-channel devices) and a serializer/deserializer baud rate of up to 17.16Gbps, enabling each application to achieve an optimal configuration.

Applications

• LiDAR
• Handheld test equipment
• Multi-channel oscilloscopes and digitizers
• Wireless communication test equipment
• Optical Coherence Tomography (OCT)
• SATCOM

Key features

• Resolution: 9-bit
• Non-interleaved architecture
• Internal dithering reduces high-order harmonics
• SNR (–1dBFS, 97MHz): 53.5dBFS
• ENOB (–1dBFS, 97MHz): 8.51 bits
• SFDR (–1dBFS, 97MHz): 64dBFS
• Noise floor (–20dBFS, 97MHz): -140.5dBFS/Hz
• Full-scale input voltage: 800mVPP-DIFF
• Full-power input bandwidth: 6GHz
• Total supported serializer/deserializer lanes: 2 to 8 (quad/dual channel) or 1 to 4 (single channel)
• Maximum baud rate: 17.16Gbps
• 64B/66B and 8B/10B encoding modes
• Subclass 1 support for deterministic latency
• Compatible with JESD204B receivers
• Optional internal sample clock generation
• Internal PLL and VCO (7.2–8.2GHz)
• SYSREF window simplifies synchronization
• Four clock outputs simplify system clocking
• Reference clock for FPGA or adjacent ADC
• Reference clock for serializer/deserializer transceivers
• Timestamp input and output for pulsed systems
• Power consumption (800MSPS):
• Quad channel: 420mW per channel
• Dual channel: 555mW per channel
• Single channel: 840mW
• Supply voltage: 1.1V/1.9V