ADC09QJ800AAVTQ1

The ADC09xJ800-Q1 is a family of 9-bit, 800MSPS quad/dual/single-channel ADCs well-suited for light detection and ranging (LiDAR) systems in automotive applications due to their low power consumption, high sample rate, and 9-bit resolution. The 6GHz full-power input bandwidth (-3dB) provides a flat frequency response for FMCW LiDAR systems and narrow pulse response for pulse-based systems. The full-power input bandwidth also supports direct RF sampling up to 4GHz. Numerous clocking features are included to relax system hardware requirements, such as an internal PLL with integrated VCO for sampling clock generation. Four clock outputs are provided to clock the logic and SerDes of an FPGA or ASIC. Timestamp inputs and outputs are provided for pulsed systems. The JESD204C serial interface reduces system size by minimizing PCB routing. The interface mode supports 2 to 8 lanes (dual- and quad-channel devices) or 1 to 4 lanes (single-channel devices) and SerDes baud rates up to 17.16Gbps, enabling optimal configuration for each application.

Applications

• LiDAR

Key features

• AEC-Q100 compliant for automotive applications: Temperature Grade 1: –40°C to +125°C, TA
• ADC core:
• Resolution: 9 bits
• Non-interleaved architecture
• Internal dither to reduce high-order harmonics
• Performance specifications:
• SNR (–1dBFS, 97MHz): 53.5dBFS
• ENOB (–1dBFS, 97MHz): 8.51 bits
• SFDR (–1dBFS, 97MHz): 64dBFS
• Noise floor (–20dBFS, 97MHz): –140.5dBFS/Hz
• Full-scale input voltage: 800mVPP-DIFF
• Full-power input bandwidth: 6GHz
• JESD204C serial data interface:
• Total support for 2 to 8 (quad/dual channel) or 1 to 4 (single channel) serializer/deserializer lanes
• Maximum baud rate: 17.16Gbps
• 64B/66B and 8B/10B encoding modes
• Subclass 1 support for deterministic latency
• Compatible with JESD204B receivers
• Optional internal sample clock generation: internal PLL and VCO (7.2–8.2GHz)
• SYSREF windowing for simplified synchronization
• Four clock outputs for simplified system clocking:
• Reference clock for FPGA or adjacent ADC
• Reference clock for serializer/deserializer transceivers
• Timestamp input and output for pulsed systems
• Power consumption (800MSPS):
• Quad channel: 420mW per channel
• Dual channel: 555mW per channel
• Single channel: 840mW
• Power supply: 1.1V/1.9V