AM3352BZCZ60

Key features

• Up to 1-GHz Sitara ARM Cortex-A8 32‑Bit RISC Processor – NEON SIMD Coprocessor – 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity) – 256KB of L2 Cache With Error Correcting Code (ECC) – 176KB of On-Chip Boot ROM – 64KB of Dedicated RAM – Emulation and Debug - JTAG – Interrupt Controller (up to 128 Interrupt Requests)
• On-Chip Memory (Shared L3 RAM) – 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM – Accessible to All Masters Supports Retention for Fast Wakeup
• External Memory Interfaces (EMIF)
• mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
• mDDR: 200-MHz Clock (400-MHz Data Rate)
• DDR2: 266-MHz Clock (532-MHz Data Rate)
• DDR3: 400-MHz Clock (800-MHz Data Rate)
• DDR3L: 400-MHz Clock (800-MHz Data Rate)
• 16-Bit Data Bus
• 1GB of Total Addressable Space
• Supports One x16 or Two x8 Memory Device Configurations
• General-Purpose Memory Controller (GPMC)
• Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
• Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
• Uses Hamming Code to Support 1-Bit ECC
• Error Locator Module (ELM)
• Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
• Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
• Supports Protocols such as EtherCAT, PROFIBUS, PROFINET, EtherNet/IP, and More
• Two Programmable Real-Time Units (PRUs)
• 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
• 8KB of Instruction RAM With Single-Error Detection (Parity)
• 8KB of Data RAM With Single-Error Detection (Parity)
• Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
• Enhanced GPIO Module Provides ShiftIn/Out Support and Parallel Latch on External Signal
• 12KB of Shared RAM With Single-Error Detection (Parity)
• Three 120-Byte Register Banks Accessible by Each PRU
• Interrupt Controller (INTC) for Handling System Input Events
• Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
• Peripherals Inside the PRU-ICSS:
• One UART Port With Flow Control Pins, Supports up to 12 Mbps
• One Enhanced Capture (eCAP) Module
• Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
• One MDIO Port
• Power, Reset, and Clock Management (PRCM) Module
• Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
• Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
• Clocks
• Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
• Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
• Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
• Power
• Two Nonswitchable Power Domains (RealTime Clock [RTC], Wake-Up Logic [WAKEUP])
• Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
• Implements SmartReflex Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
• Dynamic Voltage Frequency Scaling (DVFS)
• Real-Time Clock (RTC)
• Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
• Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
• Independent Power-on-Reset (RTC_PWRONRSTn) Input
• Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
• Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
• Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
• Peripherals
• Up to Two USB 2.0 High-Speed DRD (DualRole Device) Ports With Integrated PHY
• Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
• Integrated Switch
• Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
• Ethernet MACs and Switch Can Operate Independent of Other Functions
• IEEE 1588v2 Precision Time Protocol (PTP)
• Up to Two Controller-Area Network (CAN) Ports
• Supports CAN Version 2 Parts A and B
• Up to Two Multichannel Audio Serial Ports (McASPs)
• Transmit and Receive Clocks up to 50 MHz
• Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
• Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
• Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
• FIFO Buffers for Transmit and Receive (256 Bytes)
• Up to Six UARTs
• All UARTs Support IrDA and CIR Modes
• All UARTs Support RTS and CTS Flow Control
• UART1 Supports Full Modem Control
• Up to Two Master and Slave McSPI Serial Interfaces
• Up to Two Chip Selects
• Up to 48 MHz
• Up to Three MMC, SD, SDIO Ports
• 1-, 4- and 8-Bit MMC, SD, SDIO Modes
• MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
• Up to 48-MHz Data Transfer Rate
• Supports Card Detect and Write Protect
• Complies With MMC4.3, SD, SDIO 2.0 Specifications
• Up to Three I²C Master and Slave Interfaces
• Standard Mode (up to 100 kHz)
• Fast Mode (up to 400 kHz)
• Up to Four Banks of General-Purpose I/O (GPIO) Pins
• 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
• GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
• Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
• Eight 32-Bit General-Purpose Timers
• DMTIMER1 is a 1-ms Timer Used for Operating System