AM3352BZCZA60

Key features

• Up to 1GHz Sitara ARM Cortex-A8 32-bit RISC processor
• NEON SIMD coprocessor
• 32KB L1 instruction cache and 32KB data cache with parity
• 256KB L2 cache with ECC
• 176KB on-chip boot ROM
• 64KB dedicated RAM
• Emulation and debug — JTAG
• Interrupt controller (up to 128 interrupt requests)
• On-chip memory (shared L3 RAM)
• 64KB general-purpose OCMC RAM
• Accessible by all masters — supports retention for fast wakeup
• External Memory Interface (EMIF)
• mDDR (LPDDR), DDR2, DDR3, DDR3L controller:
• mDDR: 200MHz clock (400MHz data rate)
• DDR2: 266MHz clock (532MHz data rate)
• DDR3: 400MHz clock (800MHz data rate)
• DDR3L: 400MHz clock (800MHz data rate)
• 16-bit data bus
• 1GB total addressable space
• Supports one x16 or two x8 memory device configurations
• General-Purpose Memory Controller (GPMC)
• Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, multiplexed NOR, and SRAM)
• BCH code support with 4-bit, 8-bit, or 16-bit ECC
• Hamming code support for 1-bit ECC
• Error Location Module (ELM)
• When used with GPMC, determines error addresses in generated syndrome polynomials via BCH algorithm
• Supports 4-bit, 8-bit, and 16-bit per 512-byte block error location based on BCH algorithm
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
• Supports EtherCAT, PROFIBUS, PROFINET, EtherNet/IP, and other protocols
• Two Programmable Real-Time Units (PRUs)
• 32-bit load/store RISC processor running at 200MHz
• 8KB instruction RAM with parity
• 8KB data RAM with parity
• Single-cycle 32-bit multiplier with 64-bit accumulator
• Enhanced GPIO module with shift-in/shift-out support and parallel latch for external signals
• 12KB shared RAM with parity
• Three 120-byte register banks accessible by each PRU
• Interrupt Controller (INTC) for handling system input events
• Local interconnect bus connecting internal and external masters to PRU-ICSS internal resources
• Peripherals within PRU-ICSS:
• One UART port with flow control pins, supporting data rates up to 12Mbps
• One enhanced capture (eCAP) module
• Two MII Ethernet ports supporting industrial Ethernet (e.g., EtherCAT)
• One MDIO port
• Power, Reset, and Clock Management (PRCM) module
• Controls entry and exit of standby and deep sleep modes
• Manages sleep sequencing, power domain shutdown sequencing, wakeup sequencing, and power domain power-on sequencing
• Clocks
• Integrated high-frequency oscillator (15MHz to 35MHz) for generating reference clocks for various system and peripheral clocks
• Individual clock enable/disable control per subsystem and peripheral for reduced power consumption
• Five ADPLLs for generating system clocks (MPU subsystem, DDR interface, USB, peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], and LCD pixel clock)
• Power
• Two non-switchable power domains (RTC and WAKEUP logic)
• Three switchable power domains (MPU subsystem [MPU], SGX530 [CFX], peripherals and infrastructure [PER])
• SmartReflex Class 2B implementation for core voltage regulation based on die temperature, process variation, and performance (Adaptive Voltage Scaling [AVS])
• Dynamic Voltage and Frequency Scaling (DVFS)
• Real-Time Clock (RTC)
• Real-time date (year, month, day, and day of week) and time (hours, minutes, and seconds)
• Internal 32.768kHz oscillator, RTC logic, and 1.1V internal LDO
• Dedicated power-on reset (RTC_PWRONRSTn) input
• Dedicated input pin for external wakeup events (EXT_WAKEUP)
• Programmable alarm for generating PRCM internal interrupts (for wakeup) or Cortex-A8 internal interrupts (for event notification)
• Programmable alarm with external output (PMIC_POWER_EN) for enabling the PMIC to restore non-RTC power domains
• Peripherals
• Up to two USB 2.0 high-speed OTG ports with integrated PHY
• Up to two industrial Gigabit Ethernet MACs (10, 100, and 1000Mbps)
• Integrated switch
• Each MAC supports MII, RMII, RGMII, and MDIO interfaces
• Ethernet MAC and switch capable of running IEEE 1588v2 Precision Time Protocol (PTP) independently of other functions
• Up to two CAN ports
• Supports CAN version 2 parts A and B
• Up to two McASP ports
• Transmit and receive clocks up to 50MHz
• Up to four serial data pins per McASP port with independent TX and RX clocks
• Supports TDM, I2S, and similar formats
• Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)