ATTINY40-MMHR

ATtiny40 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny40 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny40 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of SRAM, twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 8/16-bit Timer/Counter, Internal and External Interrupts, an eight-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface, an internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the Timer/Counter, ADC, Analog Comparator, SPI, TWI, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or har

Key features

• High Performance, Low Power AVR 8 -Bit Microcontroller
• Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz
• Non-volatile Program and Data Memories – 4K Bytes of In-System Programmable Flash Program Memory – 256 Bytes Internal SRAM – Flash Write/Erase Cycles: 10,000 – Data Retention: 20 Years at 85℃ / 100 Years at 25℃
• Peripheral Features – One 8-bit Timer/Counter with Two PWM Channels – One 8/16-bit Timer/Counter – 10-bit Analog to Digital Converter • 12 Single-Ended Channels – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Master/Slave SPI Serial Interface – Slave TWI Serial Interface
• Special Microcontroller Features – In-System Programmable – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes – Enhanced Power-on Reset Circuit – Internal Calibrated Oscillator
• I/O and Packages – 20-pin SOIC: 18 Programmable I/O Lines – 20-pin TSSOP: 18 Programmable I/O Lines – 20-pad VQFN: 18 Programmable I/O Lines
• Operating Voltage: – 1.8 – 5.5V
• Programming Voltage: – 5V
• Speed Grade – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption – Active Mode: • 200 μA at 1 MHz and 1.8V – Idle Mode: • 25 μA at 1 MHz and 1.8V – Power-down Mode: • <0.1 μA at 1.8V