dsPIC33FJ64MC506-I/PT

Key features

• Up to 40 MIPS operation (at 3.0 - 3.6V)
• Industrial temperature range (-40°C to +85°C)
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Two 40-bit accumulators
• With rounding and saturation options
• Flexible and powerful addressing modes
• Indirect, Modulo and Bit-Reversed
• Software stack
• 16 × 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate
• Accumulator write back for DSP operations
• Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data
• 8-channel hardware DMA
• 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA
• Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
• Most peripherals support DMA
• 5-cycle latency
• Up to 67 available interrupt sources
• Up to five external interrupts
• Seven programmable priority levels
• Five processor exceptions
• Up to 85 programmable digital I/O pins
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
• Flash program memory, up to 256 Kbytes
• Data SRAM, up to 30 Kbytes (includes 2 Kbytes of DMA RAM)
• Flexible clock options