M0G3518QPMRQ1

The MSPM0G351x-Q1 MCUs are part of the MSP family of highly integrated, ultra-low-power 32-bit MCUs built on an enhanced Arm® Cortex®-M0+ 32-bit core platform, operating at up to 80MHz. These MCUs combine cost optimization with design flexibility for applications requiring 256KB to 512KB of flash memory in small or high pin-count packages (up to 100 pins). These devices integrate dual CAN-FD controllers, cybersecurity features, high-performance integrated analog peripherals, and excellent low-power performance across the full operating temperature range. The device offers up to 512KB of embedded flash program memory with built-in ECC, and up to 128KB of SRAM (the first 64KB with ECC and parity protection). The flash is organized into two main memory banks to support field firmware updates, with address swap support between the two main banks. Flexible cybersecurity features support secure boot, secure field firmware updates, IP protection (execute-only memory), key storage, and more. Hardware acceleration is provided for multiple AES symmetric cipher modes and a TRNG entropy source. The cybersecurity architecture is pending Arm® PSA Level 1 certification. A suite of high-performance analog modules is provided, including two simultaneously sampling 12-bit 4Msps ADCs supporting up to 27 external channels, an on-chip voltage reference (1.4V or 2.5V), a 12-bit 1Msps DAC, and three comparators operable in low-power and high-speed modes, each with an integrated 8-bit reference DAC.

Applications

• Automotive body electronics and lighting
• Automotive gateway
• Steering wheel systems
• Automotive motor control
• DC-AC inverter
• Automotive interior lighting
• Door handle module
• Kick-to-open door module
• Vehicle occupant detection
• Seat comfort module

Key features

• Arm 32-bit Cortex-M0+ CPU with memory protection unit, up to 80MHz
• Targets functional safety compliance
• Developed for functional safety applications
• Documentation to assist ISO 26262 system design will be provided
• Targets up to ASIL B systematic capability
• Targets PSA-L1 certification
• Extended operating temperature range: -40°C to 125°C
• Supply voltage range: 1.62V to 3.6V
• Up to 512KB flash with ECC
• Dual flash banks with address swapping for OTA updates
• 16KB data flash bank with ECC protection
• Total SRAM: 128KB
• SRAM (Bank 0): 64KB SRAM with ECC or hardware parity, data retention in STANDBY mode
• SRAM (Bank 1): 64KB SRAM, data retention in STOP mode
• Two simultaneously-sampling 12-bit 4Msps ADCs, up to 27 external channels
• 14-bit effective resolution at 250ksps in hardware averaging mode
• Three high-speed comparators (COMP) with integrated 8-bit reference DAC
• 32ns propagation delay in high-speed mode
• Low-power mode operation with current as low as 1μA
• One 12-bit 1Msps DAC with integrated output buffer
• Programmable analog interconnects between ADC, COMP, and DAC
• Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
• Integrated temperature sensor
• RUN mode: 123µA/MHz (CoreMark)
• SLEEP mode: 38µA/MHz
• STOP mode: 223µA (at 4MHz)
• STANDBY mode: 1.7µA (at 32kHz, with RTC, SRAM Bank 0, and state retention)
• SHUTDOWN mode: 92nA, with IO wake-up support
• 12-channel DMA controller
• Math accelerator supporting DIV, SQRT, MAC, and TRIG operations
• 9 timers, up to 28 PWM channels
• Two 16-bit general-purpose timers with QEI support
• Four 16-bit general-purpose timers for low-power operation in STANDBY mode
• One 32-bit general-purpose timer
• Two 16-bit advanced timers with dead-band support and complementary outputs, up to 12 PWM channels
• Two windowed watchdog timers (WWDT), one independent watchdog timer (IWDT)
• RTC with alarm and calendar mode
• Seven UART interfaces
• Two supporting LIN, IrDA, DALI, Smart Card, Manchester
• Three supporting low-power operation in STANDBY mode
• Three I2C interfaces, up to FM+ (1Mbit/s), SMBus/PMBus, STOP mode wake-up
• Three SPI interfaces, one up to 32Mbits/s
• Two CAN interfaces supporting CAN 2.0 A/B and CAN-FD
• Internal 4 to 32MHz oscillator (SYSOSC), accuracy up to ±1.2%
• PLL up to 80MHz output
• Internal 32kHz low-frequency oscillator (LFOSC), ±3% accuracy
• External 4 to 48MHz crystal oscillator (HFXT)
• External 32kHz crystal oscillator (LFXT)
• External clock input support
• AES-128/256 accelerator supporting GCM/GMAC, CCM/CBC-MAC, CBC, CTR
• Secure key storage for up to four AES keys
• Flexible firewall for code and data protection
• True random number generator (TRNG)
• Cyclic redundancy checker (CRC-16, CRC-32)
• Up to 94 GPIOs
• Two 5V-tolerant open-drain IOs
• Three high-drive IOs, 20mA drive strength
• Four high-speed IOs
• 2-pin serial wire debug (SWD)
• Multiple package options: 100-pin LQFP (PZ) (0.5mm pitch); 80-pin LQFP (PN) (0.5mm pitch); 64-pin LQFP (PM) (0.5mm pitch); 48-pin LQFP (PT) (0.5mm pitch); 48-pin VQFN (RGZ) (0.5mm pitch, wettable flanks); 32-pin VQFN (RHB) (0.5mm pitch, wettable flanks)
• Family members: MSPM0G3518-Q1: 256KB flash, 128KB RAM; MSPM0G3519-Q1: 512KB flash, 128KB RAM
• LP-MSPM0G3519 LaunchPad development kit and MSPM0 SDK available
• AEC-Q100 Grade 1 compliant (operating temperature -40°C to 125°C)
• Wettable flanks available on 32-pin and 48-pin VQFN packages