OMAPL137DZKB4

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

Applications

• A/V Receivers
• Automotive Amplifiers
• Soundbars
• Home Theatre Systems
• Professional Audio
• Network Streaming Audio

Key features

• Software Support – TI DSP/BIOS – Chip Support Library and DSP Library
• Dual Core SoC – 375- and 456-MHz ARM926EJ-S RISC MPU – 375- and 456-MHz C674x VLIW DSP
• ARM926EJ-S Core – 32-Bit and 16-Bit (Thumb) Instructions – DSP Instruction Extensions – Single Cycle MAC – ARM Jazelle Technology – Embedded ICE-RT for Real-Time Debug
• ARM9 Memory Architecture – 16KB of Instruction Cache – 16KB of Data Cache – 8KB of RAM (Vector Table) – 64KB of ROM
• C674x Instruction Set Features – Superset of the C67x+ and Gfx+ ISAs – Up to 3648 MIPS and 2736 MFLOPS C674x – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture – 32KB of L1P Program RAM/Cache – 32KB of L1D Data RAM/Cache – 256KB of L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Transfer Controllers – 32 Independent DMA Channels – 8 Quick DMA Channels – Programmable Transfer Burst Size
• TMS320C674x Fixed- and Floating-Point VLIW DSP Core – Load-Store Architecture with Nonaligned Support – 64 General-Purpose Registers (32-Bit) – Six ALU (32- and 40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
• Two Multiply Functional Units Mixed-Precision IEEE Floating Point Multiply Supported up to: – 2 SP x SP -> SP Per Clock – 2 SP x SP -> DP Every Two Clocks – 2 SP x DP -> DP Every Three Clocks – 2 DP x DP -> DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32x32 - Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8x8 -Bit Multiplies per Clock Cycle, and Complex Multiples – Instruction Packing Reduces Code Size – All Instructions Conditional – Hardware Support for Modulo Loop Operation – Protected Mode Operation – Exceptions Support for Error Detection and Program Redirection
• 128KB of RAM Shared Memory
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)
• Two External Memory Interfaces: – EMIFA • NOR (8- or 16-Bit-Wide Data) • NAND (8- or 16-Bit-Wide Data) • 16-Bit SDRAM with 128-MB Address Space – EMIFB • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
• Three Configurable 16550-Type UART Modules: – UART0 with Modem Control Signals – Autoflow Control Signals (CTS, RTS) on UART0 Only – 16-Byte FIFO – 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
• Two Master and Slave Inter-Integrated Circuit (I2C Bus)
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth Programmable Real-Time Unit Subsystem (PRUSS) – Two Independent Programmable Realtime Unit (PRU) Cores • 32-Bit Load and Store RISC Architecture • 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled via Software to Save Power – Standard Power-Management Mechanism • Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain – Dedicated Interrupt Controller – Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1) USB 2.0 OTG Port with Integrated PHY (USB0) – USB 2.0 High- and Full-Speed Client – USB 2.0 High-, Full-, and Low-Speed Host – End Point 0 (Control) End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs): – Six Clock Zones and 28 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable (McASP2) – FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC): – IEEE 802.3 Compliant (3.3-V I/O Only) – RMII Media-Independent Interface – Management Data I/O (MDIO) Module
• Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Three Enhanced Pulse Width Modulators (eHRPWMs): Dedicated 16-Bit Time-Base Counter with Period and Frequency Control – 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs – Dead-Band Generation – PWM Chopping by High-Frequency Carrier – Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules: – Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs – Single-Shot Capture of up to Four Event TimeStamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
• Commercial, Industrial, Extended, or Automotive Temperature