TMS320F280230DAT

The F2802x0 Piccolo series microcontrollers power the C28x core, which is coupled with highly integrated control peripherals in low-pin-count devices. The code of this series is compatible with previous C28x-based code and offers a high degree of analog integration. An internal voltage regulator allows single power rail operation. An analog comparator with an internal 10-bit reference is added and can be directly routed to control the PWM output. The ADC can perform conversion operations within a fixed full-scale range of 0 V to 3.3 V and supports proportional VREFHI/VREFLO references. The ADC interface is specifically optimized for low overhead/low latency.

Key features

• High-efficiency 32-bit CPU (TMS320C28x)
• 50-MHz and 40-MHz devices
• 3.3-V single supply
• Integrated power-on reset and brown-out reset
• Two internal zero-pin oscillators
• Up to 22 multiplexed GPIO pins
• Three 32-bit CPU timers
• On-chip Flash, SRAM, OTP memory
• Code security module
• Serial port peripherals (SCI/SPI/I2C)
• Low device and system cost:
• 3.3-V single supply
• No power supply sequencing required
• Integrated power-on and brown-out reset
• Available in small packages as few as 38 pins
• Low power
• No analog support pins
• Clocking:
• Two internal zero-pin oscillators
• Single-chip crystal oscillator/external clock input
• Dynamic PLL ratio change support
• Watchdog timer module
• Missing clock detection circuit
• Up to 22 individually programmable multiplexed GPIO pins with input filtering
• PIE module supporting all peripheral interrupts
• Three 32-bit CPU timers
• Dedicated 16-bit timer in each ePWM module
• On-chip memory:
• Flash, SRAM, OTP, boot ROM available
• 128-bit security key/lock:
• Protection of secure memory blocks
• Firmware reverse-engineering protection
• Serial port peripherals:
• One SCI (UART) module
• One SPI module
• One I2C bus
• Advanced emulation features:
• Analysis and breakpoint capability
• Real-time hardware-assisted debugging
• 2802x0 packages:
• 38-pin DA TSSOP
• 48-pin PT LQFP
• High-efficiency 32-bit CPU (TMS320C28x):
• 50 MHz (20-ns cycle time)
• 40 MHz (25-ns cycle time)
• 16 x 16 and 32 x 32 MAC operations
• 16 x 16 dual MAC
• Harvard bus architecture
• Atomic operations for fast interrupt response and processing
• Unified memory programming model
• Efficient code (using C/C++ and assembly language)
• Byte order: little-endian