TPS65580PWPR

TPS65580是一款三路、高级D-CAP2™模式同步降压转换器，可帮助系统设计人员通过成本有效性、低组件数量和低待机电流解决方案来完成多种终端设备的电源总线调节器集。主控制环路采用高级D-CAP2™模式控制，无需外部补偿组件即可提供快速的瞬态响应，能够采用低ESR输出电容器和超低ESR陶瓷电容器。此器件在输入电压为4.5V至18V之间时提供便捷和有效的运行。采用4.4mm×6.5mm 20引脚TSSOP(PWP)封装，并且额定温度范围为-40°C至85°C环境温度范围。 The TPS65580 is a 1.5A/2.5A/1.5A triple synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient response of Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. The main control loop of the TPS65580 is a fixed switching frequency PWM controller that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines constant switching frequency with an internal compensation circuit and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. TPS65580 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The TPS65580 runs with fixed frequency of 700kHz. The TPS65580 has an internal, 1.2ms, soft-start for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. The TPS65580 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. The output OCP is implemented using a cycle-by-cycle valley detect control circuit and using HICCUP mode over current protection. The switch current is monitored by measuring the low-side FET switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the onresistance of the FET. To improve accuracy, the voltage sensing is temperature compensated.

Applications

• Point-of-load regulation for low-power systems in broad applications
• Digital TV power supplies
• Networked home terminal equipment
• Digital set-top boxes (STB)
• DVD players/recorders
• Game consoles and other devices

Key features

• Advanced D-CAP2™ control mode with fast transient response, no external components required for loop compensation, compatible with ceramic output capacitors
• Wide input voltage range: 4.5V to 18V
• Output voltage range: 0.76V to 7.0V
• High-efficiency integrated FETs optimized for low duty cycle applications: 160mΩ (high-side) and 130mΩ (low-side) at 2.5A, 250mΩ (high-side) and 230mΩ (low-side) at 1.5A
• High initial reference accuracy
• Low-side RDS(on) lossless current sensing
• Fixed 1.2ms soft-start
• Non-sinking pre-bias soft-start
• 700kHz switching frequency
• Cycle-by-cycle overcurrent limit control
• OCL, OVP, UVP, UVLO, and TSD protection
• Hiccup timer for overload protection
• Power Good
• Adaptive gate driver with integrated bootstrap PMOS switch
• Constant OCP due to thermally compensated rds(on) value of 4000ppm/℃
• 20-pin HTSSOP