TI
TPS562201DDCRBuck Switching Regulator IC Adjustable 0.768V~7V 1 Output 2A SOT-6
From
₹7.51
4,69,200 in stock
2MHz Step-down type 15A LQFN-CLIP-40-EP(5x7) Voltage Regulators - DC DC Switching Regulators RoHS
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5 in stock
#C2072839
Stock & price checked 6 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹1,172.83 | ₹1,172.83 |
| 10+ | ₹1,145.39 | ₹11,453.90 |
| 30+ | ₹1,127.17 | ₹33,815.10 |
| 100+ | ₹1,108.95 | ₹1,10,895.00 |
1 × ₹1,172.83
₹1,172.83
excl. GST
₹1,383.94 incl. 18% GST
UCD74111RVFR
₹1,172.83 for 1 + GST
UCD74111是一款多芯片模块,在耐热增强型紧凑、5mm x 7mm QFN封装内集成了一个驱动器器件和两个NexFET功率MOSFET。15A输出电流能力使得此器件适合为DSP和ASIC供电。此器件被设计成为数字或模拟PWM控制器提供补充。驱动器器件的PWM输入是三态兼容的。两个驱动器电路可在同步降压电路中为高侧N通道FET开关和低侧N通道FET同步整流器提供高充放电电流。 一个用于处理外部电流感测元件上电压的精密电流感测放大器测量并监视输出电流。IMON引脚上的PWM控制器能够使用这个被放大的信号。板载比较器监视高侧开关上的电压以及外部电流感测元件上的电压,以保护功率级不受意外高电流负载的影响。一个针对高侧比较器的单个电阻器设定消隐延迟。此延迟防止错误报告与开关边沿噪声同时发生。如果发生高侧故障或过流故障,高侧FET关闭并且故障标志(FLT)被置为有效以警告PWM控制器。 The UCD74111 is a power stage for synchronous buck converter with current measurement and fault detection capabilities, making it an ideal partner for digital power controllers. This device incorporates two high-current gate drive stages, two high-performance NexFET power MOSFETs, and sophisticated current measurement circuitry that allows for the monitoring and reporting of output load current. Two separate fault detection blocks protect the power stage from excessive load current or short circuits. On-chip thermal shutdown protects the device in case of severe over-temperature conditions. The device detects faults immediately, truncates the power conversion cycle in progress without controller intervention, and asserts a digital fault flag (FLT). An on-chip linear regulator supplies the gate drive voltage. If desired, this regulator can be disabled and an external gate drive voltage can be supplied. Mode selection pins allow the device to be used in synchronous mode or independent mode. In synchronous mode, the high-side and low-side gate timing is controlled by a single PWM input. Anti-crossconduction dead-time intervals are applied automatically to the gate drives. The PWM and SRE pins directly control the high-side and low-side gate drive signals in independent mode. The automatic dead-time logic is disabled in this mode. When operating in synchronous mode, the use of the low-side FET can be disabled under the control of the SRE pin. This feature facilitates start-up into a pre-bias voltage and is also used in some applications to reduce power consumption at light loads.
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