TI
TPS562201DDCRBuck Switching Regulator IC Adjustable 0.768V~7V 1 Output 2A SOT-6
From
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4,69,200 in stock
Buck Switching Regulator IC 1 Output 25A LQFN-40-EP(5x7)
High-current, synchronous step-down power stage
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5 in stock
#C2071544
Stock & price checked 6 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹1,169.51 | ₹1,169.51 |
| 10+ | ₹1,128.55 | ₹11,285.50 |
1 × ₹1,169.51
₹1,169.51
excl. GST
₹1,380.02 incl. 18% GST
UCD74120RVFR
₹1,169.51 for 1 + GST
UCD74120是一款多芯片模块,在耐热增强型紧凑,5mm x 7mm,QFN封装内集成了一个驱动器器件和两个NexFET功率MOSFET。25A输出电流能力使得此器件适合为DSP和ASIC供电。此器件被设计成为数字或模拟PWM控制器提供补充。驱动器器件的PWM输入是三态兼容的。两个驱动器电路可在同步降压电路中为高侧N通道FET开关和低侧N通道FET同步整流器提供高充电及放电电流。 输出电流由一个用于处理外部电流感测元件上电压的精密电流感测放大器进行测量并监视。IMON引脚上的PWM控制器能够使用这个被放大的信号。板载比较器监视高侧开关上的电压以及外部电流感测元件上的电压以保护功率级不受意外高电流负载的影响。针对高侧比较器的消隐延迟由一个单电阻器设定以防止错误报告与开关边沿噪声同时发生。如果发生高侧故障或过流故障,高侧FET关闭并且故障标志(FLT)被置为有效以警告PWM控制器。 The UCD74120, a power stage for synchronous buck converter with current measurement and fault detection capabilities makes it an ideal partner for digital power controllers. This device incorporates two high-current gate drive stages, two high performance NexFET power MOSFETS and sophisticated current measurement circuitry that allows for the monitoring and reporting of output load current. Two separate fault detection blocks protect the power stage from excessive load current or short circuits. On-chip thermal shutdown protects the device in case of severe over-temperature conditions. Detected faults immediately truncate the power conversion cycle in progress, without controller intervention, and assert a digital fault flag (FLT). An on-chip linear regulator supplies the gate drive voltage. If desired, this regulator can be disabled and an external gate drive voltage can be supplied. Mode selection pins allow the device to be used in synchronous mode or independent mode. In synchronous mode, the high-side and low-side gate timing is controlled by a single PWM input. Anti-crossconduction dead-time intervals are applied automatically to the gate drives. In independent mode, the PWM and SRE pins directly control the high-side and low-side gate drive signals. Independent mode automaticly disables dead-time logic. When operating in synchronous mode, the use of the low-side FET can be disabled under the control of the SRE pin. Disablling the low-side FET facilitates start-up into a pre-bias voltage and is can reduce power consumption at light loads in some applications.
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