Varnitronics
23A256-I/SN MICROCHIP
MICROCHIP

23A256-I/SN

256Kbit SPI SOIC-8 Memory RoHS

SOIC-8ROHS3 CompliantActive

256-Kbit SPI Bus Serial SRAM

Manufacturer
MICROCHIP
Manufacturer part #
23A256-I/SN
Store part #
C615089
Package / case
SOIC-8
Category
Memory
Packaging
Tube-packed
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

45 in stock

#C615089

Stock & price checked 5 days ago

QuantityUnit pricePack price
1+₹248.86₹248.86
10+₹242.36₹2,423.60
30+₹237.97₹7,139.10
100+₹233.56₹23,356.00

1 × ₹248.86

₹248.86

excl. GST

₹293.65 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 100 per tube

23A256-I/SN

₹248.86 for 1 + GST

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Specifications

Operating Temperature
-40℃~+85℃
Features
Auto power-down function
Memory Size
256Kbit
Voltage - Supply
1.5V~1.95V;10mA
Standby Supply Current
4uA
Interface
SPI

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tube-packed
Standard pack
100 / Tube
Sold per
Piece
Minimum order
1
Unit weight
0.219 g

Overview

The 23X256 are 256-Kbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin. While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 23X256 is a 32,768-byte Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 23X256 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 23X256 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The 23A256/23K256 has three modes of operation that are selected by setting bits 7 and 6 in the STATUS register. The modes of operation are Byte, Page and Burst. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23X256 followed by the 16-bit address, with the first MSb of the address being a “don’t care” bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin.

Key features

  • Maximum Clock 20 MHz
  • Low-Power CMOS Technology:
  • Read Current: 3 mA at 1 MHz
  • Standby Current: 4 μA maximum at +85℃
  • 32,768x8 -bit Organization
  • 32-Byte Page
  • HOLD Pin
  • Flexible Operating Modes:
  • Byte read and write
  • Page mode (32-Byte Page)
  • Sequential mode
  • Sequential Read/Write
  • High Reliability
  • Temperature Ranges Supported:
  • Industrial (I): -40℃ to +85℃
  • Extended (E): -40℃ to +125℃
  • Pb-Free and RoHS Compliant, Halogen Free
  • Automotive AEC-Q100 Qualified

Alternatives

Similar parts — check the datasheet before substituting.

23A256T-I/SN#C2062581MICROCHIP · SOIC-8₹200.74 · 0 in stockView
N25S818HAS21I#C897678onsemi · SOIC-8₹249.41 · 0 in stockView

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