23K640T-I/SN

The 23X640 are 64 Kbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 23X640 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead TSSOP. The 23X640 is a 8192-byte Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 23X640 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 23X640 in HOLD mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The 23A256/23K256 has three modes of operation that are selected by setting bits 7 and 6 in the STATUS register. The modes of operation are Byte, Page and Burst. Byte Operation - is selected when bits 7 and 6 in the STATUS register are set to 00. In this mode, the read/ write operations are limited to only one byte. Page Operation - is selected when bits 7 and 6 in the STATUS register are set to 10. The 23A640/23K640 has 1024 pages of 32 Bytes. In this mode, the read and write operations are limited to within the addressed page. Sequential Operation - is selected when bits 7 and 6 in the STATUS register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23X640 followed by the 16-bit address, with the first MSB of the address being a “don't care" bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Page mode, after the first byte of data is shifted out, the next memory location on the page can be read out by continuing to provide clock pulses. This allows for 32 consecutive address reads. After the 32nd address read the internal address counter wraps back to the byte 0 address in that page.

Key features

• Max. Clock 20 MHz
• Low-Power CMOS Technology:
• Read Current: 3 mA at 1 MHz
• Standby Current: 4 μA Max. at +85℃
• 8192x8 -bit Organization
• 32-Byte Page
• HOLD pin
• Flexible Operating modes: Byte read and write, Page mode(32 Byte Page), Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported: Industrial (I): -40℃ to +85℃, Automotive (E): -40℃ to +125℃
• Pb-Free and RoHS Compliant, Halogen Free