25CSM04-I/MF

The 25CSM04 provides 4 Mbits of Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. The device is organized as 524,288 bytes of 8 bits each (512 Kbyte) and is optimized for use in consumer and industrial applications where reliable and dependable nonvolatile memory storage is essential. The 25CSM04 is capable of operation across a broad voltage range (2.5V to 5.5V). The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the HOLD pin. While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25CSM04 features a nonvolatile Security register independent of the 4 Mbit main memory array. The first half of the Security register is read-only and contains a factory-programmed, globally unique 128-bit serial number in the first 16 bytes. The 128-bit serial number is unique across the entire CS series of Serial EEPROM products and eliminates the time consuming step of performing and ensuring serialization of a product on a manufacturing line. The 128-bit read-only serial number is followed by an additional 256 bytes of user-programmable EEPROM. The user-programmable section of the Security register can later be permanently write-protected via a software sequence. The 25CSM04 features a configurable write protection scheme which allows the user to select Legacy Write Protection mode or Enhanced Write Protection mode. Legacy Write Protection mode enables the Block Protection function via the STATUS register. Enhanced Write Protection mode segments the memory into independent partitions. Each partition can be configured to inhibit writing based on the status of the Memory Partition register setting. For added reliability the 25CSM04 uses a built-in Error Correction Code (ECC) scheme. This scheme can correct up to one incorrectly read bit within four bytes read out. Additionally, the 25CSM04 includes a flag in the STATUS register to report if any errors were detected and corrected in the most recent memory array read sequence. The 25CSM04 features an identification register that contains identification information that can be read from the device. This enables the application to electronically query and identify the 25CSM04 while it is in the system. The identification method and the instruction opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor-specific Device ID, and the vendor-specific Extended Device Information (EDI).

Key features

• 4-Mbit Serial EEPROM:
• 524,288x8 organization
• Page size of 256 bytes
• Byte or sequential reads
• Byte or page writes
• Self-timed write cycle (5 ms maximum)
• Security Register:
• Preprogrammed 128-bit serial number
• 256-byte user-programmable lockable ID page
• Built-in Error Correction Code (ECC) Logic:
• ECC Status bit via the STATUS register
• JEDEC SPI Manufacturer Read ID Support
• High-Speed Clock Frequency:
• 8 MHz at VCC ≥ 3.0V
• 5 MHz at VCC ≥ 2.5V
• Legacy Write Protection Mode:
• Block protection functionality (quarter, half or entire memory array)
• Enhanced Write Protection Mode:
• User-definable memory partitions
• Each partition can be set independently and have unique protection behavior
• Low-Power CMOS Technology:
• Voltage range: 2.5V to 5.5V
• Write current: 3.0 mA at 5.0V
• Read current: 3.0 mA at 5.0V, 8 MHz
• Standby current: 1.0 μA at 2.5V (I-Temp.)
• High Reliability:
• More than one million erase/write cycles
• Built-in ECC logic for increased reliability
• Data retention: > 100 years
• ESD protection: > 4000V
• Available Temperature Ranges:
• Industrial (I): -40℃ to +85℃