AD5313BRUZ

The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisy-chaining applications using the SDO pin. The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 1.5 mW at 5 V and 0.7 mW at 3 V, reducing to 1 μW in power-down mode.

Applications

• Portable battery-powered instruments
• Digital gain and offset adjustment
• Programmable voltage and current sources
• Programmable attenuators

Key features

• AD5303: 2 buffered 8-bit DACs in 1 package A version: ±η LSB INL, B version: ±0.5 LSB INL
• AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL, B version: ±z LSB INL
• AD5323: 2 buffered 12-bit DACs in 1 package A version: ±↑6 LSB INL, B version: ±±8 LSB INL
• 16-lead TSSOP package
• Micropower operation: 300 μA @ 5 V (including reference current)
• Power-down to 200 nA @ 5 V, 50 nA @ 3 V
• 2.5 V to 5.5 V power supply
• Double-buffered input logic
• Guaranteed monotonic by design over all codes
• Buffered/unbuffered reference input options
• Output range: 0 V to VREF or 0 y to 2 VREF
• Power-on-reset to 0 V
• SDO daisy-chaining option
• Simultaneous update of DAC outputs via LDAC pin
• Asynchronous CLR facility
• Low power serial interface with Schmitt-triggered inputs
• On-chip rail-to-rail output buffer amplifiers