Varnitronics
AD9751ASTZ ADI
ADI

AD9751ASTZ

11ns 3V~3.6V Parallel port LQFP-48(7x7) Digital to Analog Converters (DAC) RoHS

LQFP-48(7x7)ROHS3 CompliantActive

AD9751 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate

Manufacturer
ADI
Manufacturer part #
AD9751ASTZ
Store part #
C578869
Package / case
LQFP-48(7x7)
Packaging
Tray
Datasheet (PDF)

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9 in stock

#C578869

Stock & price checked 24 h ago

QuantityUnit pricePack price
1+₹6,169.25₹6,169.25
30+₹5,961.81₹1,78,854.30

1 × ₹6,169.25

₹6,169.25

excl. GST

₹7,279.71 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 250 per tray

AD9751ASTZ

₹6,169.25 for 1 + GST

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Specifications

Settling Time
11ns
Operating Temperature
-40℃~+85℃
Voltage - Supply
3V~3.6V
Function
Integrated phase-locked loop;Built-in reference source;Differential output
Integral non - linearity
0.3LSB;0.2LSB
Number of Channels
1
Resolution (Bits)
10;300MHz
Interface Type
Parallel port

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tray
Standard pack
250 / Tray
Sold per
Piece
Minimum order
1
Unit weight
0.808 g

Overview

The AD9751 is a dual muxed port, ultrahigh speed, single-channel, 10-bit CMOS DAC. It integrates a high quality 10-bit TxDAC+ core, a voltage reference, and digital interface circuitry into a small 48-lead LQFP package. The AD9751 offers exceptional ac and dc performance while supporting update rates up to 300 MSPS. The AD9751 has been optimized for ultrahigh speed applications up to 300 MSPS where data rates exceed those possible on a single data interface port DAC. The digital interface consists of two buffered latches as well as control logic. These latches can be time multiplexed to the high speed DAC in several ways. This PLL drives the DAC latch at twice the speed of the externally applied clock and is able to interleave the data from the two input channels. The resulting output data rate is twice that of the two input channels. With the PLL disabled, an external 2x clock may be supplied and divided by two internally. The CLK inputs (CLK + /CLK–) can be driven either differentially or single-ended, with a signal swing as low as 1 Vp-p. The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Differential current outputs support single-ended or differential applications. The differential outputs each provide a nominal full-scale current from 2 mA to 20 mA. The AD9751 is manufactured on an advanced low cost 0.35 µm CMOS process. It operates from a single supply of 3.0 V to 3.6 V and consumes 155 mW of power.

Applications

  • Communications: LMDS, LMCS, MMDS
  • Base Stations
  • Digital Synthesis
  • QAM and OFDM

Key features

  • 10-Bit Dual Muxed Port DAC
  • 300 MSPS Output Update Rate
  • Excellent SFDR and IMD Performance
  • SFDR to Nyquist @ 25 MHz Output: 64 dB
  • Internal Clock Doubling PLL
  • Differential or Single-Ended Clock Input
  • On-Chip 1.2x Reference
  • Single 3.3V Supply Operation
  • Power Dissipation: 155 mW @ 3.3 V
  • 48-Lead LQFP

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