AM6251ASGGHAALWR

Key features

• Processor Cores:
• Up to quad-core 64-bit Arm® Cortex®-A53 microprocessor subsystem, up to 1.4GHz
• Quad-core Cortex-A53 cluster (with 512KB L2 shared cache, including SECDED ECC)
• Each A53 core includes 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with parity protection
• Single-core Arm® Cortex®-M4F MCU up to 400MHz
• 256KB SRAM with SECDED ECC
• Dedicated device/power manager
• Multimedia:
• Display subsystem
• Dual display support
• 1920x1080 @ 60fps per display
• 1x 2048x1080 + 1x 1280x720
• Pixel clock support up to 165MHz, independent PLL per display
• OLDI (4-lane LVDS - 2x) and DPI (24-bit RGB LVCMOS)
• Safety features including frame detection and MISR data checking
• 3D GPU
• 1 pixel per clock or higher
• Fill rate >500 Megapixels/s
• >500MTexels/s, >8GFLOPs
• Minimum 2 composition layers
• Resolution up to 2048x1080 @60fps
• ARGB32, RGB565, and YUV format support
• 2D graphics support
• OpenGL ES 3.1, Vulkan 1.2
• One 4-lane Camera Serial Interface (CSI-Rx) with DPHY
• MIPI® CSI-2 v1.3 compliant + MIPI D-PHY 1.2
• 1, 2, 3, or 4 data lane modes, up to 1.5Gbps per lane
• ECC verification/correction and CRC check + ECC on RAM
• Virtual channel support (up to 16)
• DMA direct write of streaming data to DDR
• Memory Subsystem:
• Up to 816KB on-chip RAM
• 64KB on-chip RAM (OCSRAM) with SECDED ECC, partitionable into smaller memory banks in 32KB increments, supporting up to 2 independent memory banks
• 256KB on-chip RAM with SECDED ECC in SMS subsystem
• 176KB on-chip RAM with SECDED ECC in SMS subsystem for TI security firmware
• 256KB on-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
• 64KB on-chip RAM with SECDED ECC in device/power manager subsystem
• DDR Subsystem (DDRSS)
• LPDDR4 and DDR4 memory type support
• 16-bit data bus with inline ECC
• Speed up to 1600MT/s
• Maximum addressable range: 8GBytes with DDR4; 4GBytes with LPDDR4
• Functional Safety:
• Targeting compliance with functional safety standards [Automotive]
• Developed for functional safety applications
• Documentation provided to assist ISO 26262-compliant functional safety system design
• System capable of meeting ASIL D requirements
• Targeting hardware integrity up to ASIL B
• Safety-related certifications
• ISO 26262 certification by TUV SUD planned
• AEC-Q100 compliant
• Security:
• Secure boot support
• Hardware-enforced Root of Trust (RoT)
• RoT transfer via backup key support
• Takeover protection, IP protection, and anti-rollback protection
• Trusted Execution Environment (TEE) support
• Arm TrustZone®-based TEE
• Extensive firewall support for isolation
• Secure watchdog/timer/IPC
• Secure storage support
• Replay Protected Memory Block (RPMB) support
• Dedicated security controller with user-programmable HSM core, dedicated secure DMA and IPC subsystem for isolated processing
• Cryptographic acceleration support
• Session-aware cryptographic engine with automatic key material switching based on input data stream
• Cryptographic core support
• AES – 128/192/256-bit key sizes
• SHA2 – 224/256/384/512-bit key sizes
• DRBG with true random number generator
• PKA (Public Key Accelerator) for RSA/ECC processing, supporting secure boot
• Debug security
• Debug access under secure software control
• Security-aware debug
• PRU Subsystem:
• Dual-core Programmable Real-Time Unit Subsystem (PRUSS) up to 333MHz
• GPIO drive for cycle-accurate protocols: GPIO; UART; I2C; external ADC
• 16KB program memory per PRU with SECDED ECC
• 8KB data memory per PRU with SECDED ECC
• 32KB shared memory with SECDED ECC
• CRC32/16 hardware accelerator
• Scratch pad memory with 3 banks of 30 x 32-bit registers
• 1 industrial 64-bit timer with 9 capture events, 16 compare events, and slow/fast compensation
• 1 interrupt controller (INTC) supporting minimum 64 input events
• High-Speed Interfaces:
• Integrated Ethernet switch support (2 external ports total)
• RMII (10/100) or RGMII (10/100/1000)
• IEEE1588 (Annex D, E, and F, and 802.1AS PTP)
• Clause 45 MDIO PHY management
• ALE engine-based packet classifier with 512 classifiers
• Priority-based flow control
• Time-Sensitive Networking (TSN) support
• Four CPU hardware interrupt pacing
• IP/UDP/TCP checksum offload in hardware
• Two USB2.0 ports
• Configurable as USB host, USB peripheral, or USB dual-role device (DRD mode)
• Integrated USB VBUS detection
• General Connectivity:
• 9 UART controllers
• 5 SPI controllers
• 6 I2C ports
• 3 McASP ports
• TX and RX clock up to 50MHz
• Up to 4/6/16 serial data pins with independent TX and RX clocks across 3 McASPs
• TDM, I2S, and similar format support
• Digital audio interface transmission support (SPDIF, IEC60958-1, and AES-3 formats)
• FIFO buffers for TX and RX (256 bytes)
• Audio reference output clock support
• 3 ePWM modules
• 3 eQEP modules
• 3 eCAP modules
• GPIO — all LVCMOS I/Os configurable as GPIO
• 3 CAN-FD-capable CAN modules
• CAN protocol 2.0A, 2.0B, and ISO 11898-1 compliant
• Full CAN FD support (up to 64 data bytes)
• Parity/ECC checking on message RAM
• Speed up to 8Mbps
• Media and Data Storage:
• 3 MMC/SD®/SDIO interfaces
• 1x 8-bit eMMC interface up to HS200
• 2x 4-bit SD/SDIO interfaces up to UHS-I
• eMMC 5.1, SD 3.0, and SDIO 3.0 compatible
• 1 GPMC up to 133MHz
• Flexible 8-bit and 16-bit asynchronous memory interface with up to four chip selects (22-bit address) (NAND, NOR, Muxed-NOR, and SRAM)
• 4-bit, 8-bit, or 16-bit ECC using BCH code
• 1-bit ECC using Hamming code
• Error Location Module (ELM) used with GPMC to locate addresses of data errors from companion polynomials (generated when using BCH algorithm)
• 4-bit, 8-bit, and 16-bit per 512-byte block error location per BCH algorithm
• OSPI/QSPI with DDR/SDR support
• Serial NAND and serial NOR flash device support
• 4GB memory address support
• XIP mode with optional real-time encryption