AT89C51CC02CA-SISUM

- EEPROM – EEPROM Data Cannot be Accessed from the Boot Area (FM1) EEPROM Data cannot be read or written from the boot area (FM1). - XRAM – P3.7 and P3.6 Signals are Generated: When an overflow access is detected on the XRAM during a Movx instruction, negative pulses on the P3.7 and P3.6 signals are generated. - Double IT on External Falling Edge On INT1 or INT0 in X2 Mode: When CPU is in X2 Mode and Timer 1 or Timer 0 in X1 Mode (CKCON = 0x7F), IEx flag is not cleared by hardware after a service interrupt. In this case, the CPU executes the ISR a second time. - Timer 2 (Baud Rate Generator Mode) – No IT When TF2 is Set by Software: When Timer 2 is used in baud rate generator mode, setting TF2 does not generate an interrupt. - Timer 2 (Baud Rate Generator Mode) – Long Start Time: When Timer 2 is used as baud rate generator, TH2 is not loaded with RACP2H at the beginning, then UART is not operational before almost 10,000 machine cycles. - UART - RB8 Lost With JBC on SCON Register: When using the JBC instruction on any bit of SCON register, if RB8 changes from 1 to 0, the 0 bit can be lost. - CAN – CANCONCH Harmless Corruption: When a stuff error occurs during a CAN frame transmission on DPRAM write access, the CONCH1, CONCH0 bits in CANCONCH are corrupted. This corruption has no effect on the correct behavior of the Transmit channel. - ADC - Interrupt Controller/ADC Idle Mode/Loops In High Priority Interrupt: The problem occurs during an A/D conversion in idle mode, if a hardware interrupt occurs followed by a second interrupt with higher priority before the end of the A/D conversion. If the above configuration occurs, the highest priority interrupt is served immediately after the A/D conversion. At the end of the highest priority interrupt service, the processor will not serve the hardware reset interrupt pending. It will also not serve any new interrupt requests with a priority lower than the high level priority last served. - Flash/EEPROM – First Read After Load Disturbed: In the "In - Application Programming" mode from the Flash, if the User software application load the Column Latch Area prior to call the programming sequence in the CAN Bootloader, it leads to a wrong Opcode Fetch during the column latch load sequence. - CAN – Sporadic Errors: When BRP = 0 or when BRP>0 and SMP = 0, the CAN controller may de - synchronize and send one error frame to ask for the retransmission of the incoming frame, even though it had no error. This is likely to occur with BRP = 0 or after long inter - frame periods without synchronization (low bus load). The CAN macro can still properly synchronize on frames following the error. - C51 Core – Bad Exit of Power - down in X2 Mode: When exiting power - down mode by interrupt while CPU is in X2 mode, it leads to bad execution of the first instruction run when CPU restarts. - Timer0/1 – Extra Interrupt: When the Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra interrupt may randomly occurred for Timer0 or Timer1. - Transmission after a 3 bit Intermessage: If a Transmit Message Object (MOB) is enabled while the CAN bus is busy with an on - going message, the transmitter will wait for the 3 - bit Intermission before starting its transmission. If the transmitter lost arbitration against another node, two conditions can occur: 1. At least one Receive MOB of the chip are programmed to accept the incoming message. In this case, the transmitter will wait for the next 3 - bit Intermission to retry its transmission. 2. No Receive MOB of the chip are programmed to accept the incoming message. In this case the transmitter will wait for a 4 - bit Intermission to retry its transmission. In this case, any other CAN nodes ready to transmit after a 3 - bit Intermission will start transmit before the chip transmitter, even if their messages have lower priority IDs.