ATSAMV71N20B-AABT

Key features

• Arm Cortex-M7 running at up to 300 MHz
• 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)
• Single-precision and double-precision HW Floating Point Unit (FPU)
• Memory Protection Unit (MPU) with 16 zones
• DSP Instructions, Thumb-2 Instruction Set
• Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)
• Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data
• Up to 384 Kbytes embedded Multi-port SRAM
• Tightly Coupled Memory (TCM)
• 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines
• 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling
• Embedded voltage regulator for single-supply operation
• Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation
• Quartz or ceramic resonator oscillators: 3 MHz to 20 MHz main oscillator with failure detection, 12 MHz or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock
• RTC with Gregorian calendar mode, waveform generation in low-power modes
• RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations
• 32-bit low-power Real-time Timer (RTT)
• High-precision Main RC oscillator with 12 MHz default frequency
• 32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock (SLCK)
• One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations
• Temperature Sensor
• One dual-port 24-channel central DMA Controller (XDMAC)
• Low-power sleep, wait and backup modes, with typical power consumption down to 1.1 μA in Backup mode with RTC, RTT and wakeup logic enabled
• Ultra low-power RTC and RTT
• 1 Kbyte of backup RAM (BRAM) with dedicated regulator
• One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE 1588 PTP frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping and IEEE802.1Qav credit-based traffic-shaping hardware support.
• USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA
• 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
• Two host Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission
• MediaLB device with 3-wire mode, up to 1024x Fs speed, supporting MOST25 and MOST50 networks
• Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, rDA, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode.
• Five 2-wire UARTs with SleepWalking support
• Three Two-Wire Interfaces (TWIHS) (I²C-compatible) with SleepWalking support
• Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and on-the-fly scrambling
• Two Serial Peripheral Interfaces (SPI)
• One Serial Synchronous Controller (SSC) with I2S and TDM support
• Two Inter-IC Sound Controllers (I2SC)
• One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
• Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
• Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control
• Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error correction feature.
• One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over Sampling modes
• One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
• True Random Number Generator (TRNG) AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
• Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
• Five Parallel Input/Output Controllers (PIO)
• Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices
• Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices