ATTINY826-MU

The ATtiny424/426/427 and ATtiny824/826/827 microcontrollers of the tinyAVR 2 family are using the AVR CPU with hardware multiplier, running at up to 20 MHz, with 4/8 KB Flash, 512B/1 KB of SRAM, and 128B of EEPROM available in a 14-, 20-, and 24-pin package. The family uses the latest technologies from Microchip with a flexible and low-power architecture, including an Event System, advanced digital peripherals, and accurate analog features such as a 12-bit differential ADC with Programmable Gain Amplifier(PGA).

Key features

• High-Performance Low-Power AVR CPU
• Running at up to 20 MHz
• Single-cycle I/O access
• Two-level interrupt controller with vectored interrupts
• Two-cycle hardware multiplier
• Supply voltage range: 1.8V to 5.5V
• Memories
• 4/8 KB In-System self-programmable Flash memory
• 512B/1 KB SRAM
• 128B EEPROM
• 32B of user row in nonvolatile memory that can keep data during chip-erase and be programmed while the device is locked
• Write/erase endurance
• Flash 10,000 cycles
• EEPROM 100,000 cycles
• Data retention: 40 years at 55℃
• System
• Power-on Reset (POR)
• Brown-out Detection (BOD)
• Clock options
• Lockable 20 MHz Low-Power internal oscillator
• 32.768 kHz Ultra-Low Power (ULP) internal oscillator
• 32.768 kHz external crystal oscillator
• External clock input
• Single-pin Unified Program and Debug Interface (UPDI)
• Three sleep modes
• Idle with all peripherals running and immediate wake-up time
• Standby with configurable operation of selected peripherals
• Power-Down with full data retention
• Peripherals
• One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three PWM channels
• Two 16-bit Timer/Counters type B (TCB) with input capture and simple PWM functionality
• One 16-bit Real-Time Counter (RTC) running from external 32.768 kHz crystal or internal 32.768 kHz ULP oscillator
• Two Universal Synchronous Asynchronous Receiver Transmitters (USART) with fractional baud rate generator, auto-baud, and start-of-frame detection
• Host/Client Serial Peripheral Interface (SPI)
• Host/Client Two-Wire Interface (TWI) with dual address match
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
• Event System for CPU independent and predictable inter-peripheral signaling
• Configurable Custom Logic (CCL) with four programmable Look-Up Tables (LUT)
• One Analog Comparator (AC) with scalable reference input
• One 12-bit differential 375 ksps Analog-to-Digital Converter (ADC) with Programmable Gain Amplifier (PGA) and up to 15 input channels
• Multiple internal voltage references
• 1.024V
• 2.048V
• 2.500V
• 4.096V
• VDD
• Automated Cyclic Redundancy Check (CRC) flash memory scan
• Watchdog Timer (WDT) with Window Mode, with a separate on-chip oscillator
• External interrupt on all general purpose pins
• I/O and Packages
• Up to 22 programmable I/O pins
• 14-pin
• SOIC
• TSSOP
• 20-pin
• SOIC
• SSOP
• VQFN 3x3 mm
• 24-pin
• VQFN 4x4 mm
• Temperature Ranges
• -40℃ to 85℃ (industrial)
• -40℃ to 125℃ (extended)
• Speed Grades (-40℃ to 85℃)
• 0-5 MHz @ 1.8V - 5.5V
• 10 MHz @ 2.7V - 5.5V
• 20 MHz @ 4.5V - 5.5V
• Speed Grades (-40℃ to 125℃)
• 0-8 MHz @ 2.7V - 5.5V
• 0-16 MHz @ 4.5V - 5.5V