ATTINY88-MUR

The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The device includes the following modes for saving power: • Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning • ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC • Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits.

Key features

• Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32×8 General Purpose Working Registers – Fully Static Operation
• High Endurance Non-volatile Memory Segments – 4K/8K Bytes of In-System Self-Programmable Flash Program Memory – 64/64 Bytes EEPROM – 256/512 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 years at 85℃ / 100 years at 25℃ – Programming Lock for Software Security
• One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
• One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes
• 6- or 8-channel 10-bit ADC
• Master/Slave SPI Serial Interface
• Byte-oriented 2-wire Serial Interface (Philips I²C Compatible)
• Programmable Watchdog Timer with Separate On-Chip Oscillator
• On-Chip Analog Comparator
• Interrupt and Wake-up on Pin Change
• Special Microcontroller Features – debugWIRE On-Chip Debug System – In-System Programmable via SPI Port – Power-On Reset and Programmable Brown-Out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down – On-Chip Temperature Sensor
• I/O and Packages – 24 Programmable I/O Lines: • 28-pin PDIP • 28-pad QFN
• 28 Programmable I/O Lines: • 32-lead TQFP • 32-pad QFN • 32-ball UFBGA
• Operating Voltage: – 1.8 – 5.5V
• Temperature Range: – -40℃ to ±85℃
• Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 – 5.5V
• Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240 μA – Power-Down Mode: 0.1 μA at 1.8V