ATXMEGA256D3-AUR

The AVR XMEGA D microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AVR XMEGA D devices achieve throughputs approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA D devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller; up to 50 general purpose I/O lines; 16-bit real-time counter (RTC); up to five flexible, 16-bit timer/counters with capture, compare and PWM modes; up to three USARTs; two I²C and SMBUS compatible two-wire serial interfaces (TWIs); up to two serial peripheral interfaces (SPIs); CRC module; one 16-channel, 12-bit ADC with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The Atmel AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pinchange interrupt.

Key features

• in-system programmable flash with read-while-write capabilities
• internal EEPROM and SRAM
• four-channel event system and programmable multilevel interrupt controller
• up to 50 general purpose I/O lines
• 16-bit real-time counter (RTC)
• up to five flexible, 16-bit timer/counters with capture, compare and PWM modes
• up to three USARTs
• two I²C and SMBUS compatible two-wire serial interfaces (TWIs)
• up to two serial peripheral interfaces (SPIs)
• CRC module
• one 16-channel, 12-bit ADC with programmable gain
• two analog comparators (ACs) with window mode
• programmable watchdog timer with separate internal oscillator
• accurate internal oscillators with PLL and prescaler
• programmable brown-out detection
• fast, two-pin program and debug interface (PDI)
• five software selectable power saving modes