CD4019BM96

4.2mA 30uA 4.2mA 3V~18V 4 SOIC-16 Gates and Inverters - Multi-Function, Configurable RoHS

SOIC-16ROHS3 CompliantActive

CMOS Quad AND/OR Select Gate

Manufacturer: TI
Manufacturer part #: CD4019BM96
Store part #: C2878073
Package / case: SOIC-16
Category: Gates and Inverters - Multi-Function, Configurable
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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3,357 in stock

#C2878073

Stock & price checked 3 days ago

Quantity	Unit price	Pack price
1+	₹58.33	₹58.33
10+	₹46.62	₹466.20
30+	₹40.76	₹1,222.80
100+	₹35.79	₹3,579.00
500+	₹34.27	₹17,135.00
1,000+	₹33.39	₹33,390.00

Quantity (min 1)

1 × ₹58.33

₹58.33

excl. GST

₹68.83 incl. 18% GST

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Standard pack: 2,500 per reel

CD4019BM96

₹58.33 for 1 + GST

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Specifications

Input Logic Level - High: 3.5V;7V;11V
Input Logic Level - Low: 1.5V;3V;4V
Logic Family: 4000B Series
Propagation Delay: 100ns@15V
Current - Output Low(IOL): 4.2mA
Output Logic Level - High: 4.95V;9.95V;14.95V
Quiescent Current(Iq): 30uA
Current - Output High(IOH): 4.2mA
Voltage - Supply: 3V~18V
Operating Temperature: -55℃~+125℃
Number of Gates: 4
Output Logic Level - Low: 50mV

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
Moisture sensitivity: MSL 1 (unlimited)
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 2,500 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.284 g

Overview

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

Applications

AND-OR select gating
Shift-right/shift-left registers
True/complement selection
AND/OR/Exclusive-OR selection

Key features

Medium-speed operation: tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25℃
Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V

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