CD74HC595M96

The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear overline{SRCLR} input, serial (SER) input, and serial output for cascading. When the output-enable overline{OE} input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

Key features

• 8-bit serial-in, parallel-out architecture
• Operating voltage range: 2V~6V
• High-current 3-state outputs, capable of driving up to 15 LSTTL loads
• Low power consumption, max supply current Icc of 80μA
• Typical propagation delay tpd of 14ns
• Output drive current ±6mA at 5V supply voltage
• Max input current 1μA
• Shift register with direct clear function
• Max supply voltage range: -0.5V~7V
• Max input clamp current ±20mA
• Max output clamp current ±20mA
• Max continuous output current ±35mA
• Max continuous current through VCC or GND: ±70mA
• Storage temperature range: -65℃~150℃
• Thermal impedance by package: E package 67℃/W, DW package 57℃/W, M package 73℃/W, NS package 64℃/W, SM package 82℃/W