CYT3DLBBHBQ1BZSGS

CYT3DL is a family of TRAVEO T2G microcontrollers targeted at automotive systems such as instrument clusters and Head- Up Displays (HUD). CYT3DL has a 2D Graphics engine, sound processing, an Arm Cortex- M7 CPU for primary processing, and an Arm Cortex- M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), Clock Extension Peripheral Interface (CXPI), and Ethernet. TRAVEO T2G devices are manufactured on an advanced 40- nm process. CYT3DL incorporates low- power flash memory, multiple high- performance analog and digital peripherals, and enables the creation of a secure computing platform.

Key features

• Graphics subsystem
• Supports 2D and 2.5D (perspective warping, 3D effects) graphics rendering
• Internal color resolution: 40-bit for RGBA (4 × 10-bit), 24-bit for RGB (3 × 8-bit)
• 2048 KB of embedded video RAM memory (VRAM)
• Two video output interfaces supporting a display from Parallel RGB (max display size: 600 × 600 at 40 MHz), FPD-link single (max display size: 1920 × 720 at 110 MHz)
• One Capture engine for video input processing for ITU 656 or parallel RGB/YUV or MIPI CSI-2 input (ITU656: up to 800 × 480, multiplexed with RGB interface; RGB: max capture size 1600 × 600 at 80 MHz; Two-/four-lane MIPI CSI-2 interface: max capture size 1920 × 720 for two lanes at 110 MHz, 2880 × 1080 for four lanes at 220 MHz)
• Display warping on-the-fly for HUD applications
• Direct video feed through from capture to display interface with graphics overlay
• Composition engine for scene composition from display layers
• Display engine for video timing generation and display functions
• Drawing engine for acceleration of vector graphics rendering
• Command sequencer for setup and control of the rendering process
• Supports graphics rendering without frame buffers (on-the-fly)
• Single-channel FPD-Link/LVDS interface for up to HD resolution video output
• Sound subsystem
• Four time-division multiplexing (TDM) interfaces
• Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces
• Up to five sound generator (SG) interfaces
• Two PCM Audio stream mixers with five input streams
• One audio digital-to-analog converter (DAC)
• CPU subsystem
• 240-MHz (max) 32-bit Arm Cortex-M7 CPU, with single-cycle multiply, single/double-precision floating point unit (FPU), 16-KB data cache, 16-KB instruction cache, memory protection unit (MPU), 64-KB instruction and 64-KB data Tightly-Coupled Memories (TCM)
• 100-MHz 32-bit Arm Cortex-M0+ CPU with single-cycle multiply, memory protection unit, inter-processor communication in hardware, four DMA controllers (Peripheral DMA controller #2 (P-DMA0) with 76 channels, Peripheral DMA controller #1 (P-DMA1) with 84 channels, Memory DMA (AHB) controller (M-DMA0) with 8 channels, Memory DMA (AXI) controller (M-DMA1) with 4 channels)
• Integrated memories
• 4160-KB code-flash with an additional 128-KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
• 384-KB SRAM with selectable retention granularity
• Crypto engine
• Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
• Secure boot and authentication using digital signature verification, using fast secure boot
• AES: 128-bit blocks, 128-/192-/256-bit keys
• 3DES: 64-bit blocks, 64-bit key
• Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC)
• SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
• CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
• True random number generator (TRNG) and pseudo random number generator (PRNG)
• Galois/Counter Mode (GCM)
• Functional safety for ASIL-B
• Memory protection unit (MPU)
• Shared memory protection unit (SMPU)
• Peripheral protection unit (PPU)
• Watchdog timer (WDT)
• Multi-counter watchdog timer (MCWDT)
• Low-voltage detector (LVD)
• Brown-out detection (BOD)
• Overvoltage detection (OVD)
• Overcurrent detection (OCD)
• Clock supervisor (CSV) (Supported in all power modes except Hibernate mode)
• Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-power 2.7 V to 5.5 V operation
• Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management
• Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA_ADC
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup support
• Up to four pins to wakeup from Hibernate mode
• Up to 61 GPIO pins to wakeup from DeepSleep mode
• Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clocks
• Internal main oscillator (IMO)
• Internal low-speed oscillator (ILO)
• External crystal oscillator (ECO)
• Watch crystal oscillator (WCO)
• Phase-locked loop (PLL)
• Frequency-locked loop (FLL)
• Low-power external crystal oscillator (LPECO)
• Communication interfaces
• Up to four CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and