dsPIC30F2012-30I/SO

Key features

• Modified Harvard architecture
• C compiler optimized instruction set architecture
• Flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Up to 24 Kbytes on-chip Flash program space
• Up to 2 Kbytes of on-chip data RAM
• Up to 1 Kbyte of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPS operation: DC to 40 MHz external clock input; 4 MHz - 10 MHz oscillator input with PLL active (4x, 8x, 16x)
• Up to 21 interrupt sources: 8 user-selectable priority levels; 3 external interrupt sources; 4 processor trap sources
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier
• All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation
• Single-cycle ±16 shift
• High-current sink/source I/O pins: 25 mA/25 mA
• Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• 3-wire SPI modules